Patents by Inventor Atsuo Isobe
Atsuo Isobe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7541228Abstract: An object of the present invention is to provide a semiconductor device formed by laser crystallization by which formation of grain boundaries in the TFT channel formation region can be avoided, and a method of manufacturing the same. Still another object of the present invention is to provide a method of designating the semiconductor device.Type: GrantFiled: January 4, 2008Date of Patent: June 2, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kiyoshi Kato, Toshihiko Saito, Atsuo Isobe, Toru Takayama, Junya Maruyama, Yuugo Goto, Yumiko Ohno
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Patent number: 7541618Abstract: To provide a liquid crystal display device having high quality display with a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a layer that is different from a gate electrode so that the capacitor wiring is arranged in parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of adjacent pixels can be avoided, thereby obtaining satisfactory display images.Type: GrantFiled: October 15, 2007Date of Patent: June 2, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroshi Shibata, Atsuo Isobe
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Patent number: 7538350Abstract: It is a problem to provide a semiconductor device production system using a laser crystallization method capable of preventing grain boundaries from forming in a TFT channel region and further preventing conspicuous lowering in TFT mobility due to grain boundaries, on-current decrease or off-current increase. An insulation film is formed on a substrate, and a semiconductor film is formed on the insulation film. Due to this, preferentially formed is a region in the semiconductor film to be concentratedly applied by stress during crystallization with laser light. Specifically, a stripe-formed or rectangular concavo-convex is formed on the semiconductor film. Continuous-oscillation laser light is irradiated along the striped concavo-convex or along a direction of a longer or shorter axis of rectangle.Type: GrantFiled: January 29, 2007Date of Patent: May 26, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Koji Dairiki, Hiroshi Shibata, Chiho Kokubo, Tatsuya Arao, Masahiko Hayakawa, Hidekazu Miyairi, Akihisa Shimomura, Koichiro Tanaka, Shunpei Yamazaki, Mai Akiba
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Patent number: 7537979Abstract: Since sodium contained in glass, or glass itself has low heat resistance; a CPU fabricated using a TFT formed over a glass substrate or the like has not been obtained. In the case of operating a CPU with high-speed, the length of a gate (gate length) of a TFT is required to be shorter. However, since a glass substrate has large deflection, a gate electrode cannot have been etched to have a gate length short enough to be used for a CPU. According to the invention, a conductive film is formed over a crystalline semiconductor film formed over a glass substrate, a mask is formed over the conductive film, and the conductive film is etched by using the mask; thus, a thin film transistor with a gate length of 1.0 ?m or less is formed. In particular, the crystalline semiconductor film is formed by crystallizing an amorphous semiconductor film formed over a glass substrate by laser irradiation.Type: GrantFiled: August 24, 2006Date of Patent: May 26, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Satoru Saito, Saishi Fujikawa
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Patent number: 7534705Abstract: An impurity of one conductivity type is ionized and accelerated by electric field before being implanted into a semiconductor layer to form a high concentration impurity region near its surface. Then the semiconductor layer is irradiated with continuous wave laser light for melting and crystallization or recrystallization, through which a region where the concentration of the impurity is constant is formed in the semiconductor layer. The continuous wave laser light irradiation may bring the semiconductor layer to the crystalline phase from the amorphous phase as long as the impurity element is re-distributed. The impurity is segregated through this process to newly create a high concentration region. However, this region is removed and no problem arises.Type: GrantFiled: October 30, 2007Date of Patent: May 19, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akihisa Shimomura, Osamu Nakamura, Tatsuya Arao, Hidekazu Miyairi, Atsuo Isobe, Tamae Takano, Kouki Inoue
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Publication number: 20090098720Abstract: A manufacturing method of a semiconductor device of the present invention includes the steps of forming a first insulating film over a substrate, forming a semiconductor film over the first insulating film, oxidizing or nitriding the semiconductor film by conducting a plasma treatment to the semiconductor film under a condition of an electron density of 1×1011 cm?3 or more and 1×1013 cm?3 or less and an electron temperature of 0.5 eV or more and 1.5 eV or less, using a high frequency wave, forming a second insulating film to cover the semiconductor film, forming a gate electrode over the second insulating film, forming a third insulating film to cover the gate electrode, and forming a conductive film over the third insulating film.Type: ApplicationFiled: December 15, 2008Publication date: April 16, 2009Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo ISOBE, Satoshi MURAKAMI, Tamae TAKANO, Shunpei YAMAZAKI
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Publication number: 20090078970Abstract: A semiconductor device is demonstrated in which a plurality of field-effect transistors is stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. Each of the plurality of filed-effect transistors has a semiconductor layer which is prepared by a process including separation of the semiconductor layer from a semiconductor substrate followed by bonding thereof over the substrate. Each of the plurality of field-effect transistors is covered with an insulating film which provides distortion of the semiconductor layer. Furthermore, the crystal axis of the semiconductor layer, which is parallel to the crystal plane thereof, is set to a channel length direction of the semiconductor layer, which enables production of the semiconductor device with high performance and low power consumption having an SOI structure.Type: ApplicationFiled: September 12, 2008Publication date: March 26, 2009Applicant: Semiconductor Energy Laboratory Co., LtdInventors: Shunpei YAMAZAKI, Atsuo ISOBE, Hiromichi GODO, Yutaka OKAZAKI
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Publication number: 20090079000Abstract: An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.Type: ApplicationFiled: September 12, 2008Publication date: March 26, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Atsuo ISOBE, Hiromichi GODO, Yutaka OKAZAKI
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Patent number: 7507995Abstract: An insulating film with a linear concave portion is formed and a semiconductor film is formed thereon by deposition. The semiconductor film is irradiated with laser light to melt the semiconductor film and the melted semiconductor is poured into the concave portion, where it is crystallized. This makes distortion or stress accompanying crystallization concentrate on other regions than the concave portion. A surface of this crystalline semiconductor film is etched away, thereby forming in the concave portion a crystalline semiconductor film which is covered with side walls of the concave portion from the sides and which has no other grain boundaries than twin crystal. TFTs and memory TFTs having this crystalline semiconductor film as their channel regions are highly reliable, have high field effect mobility, and are less fluctuated in characteristic. Accordingly, a highly reliable semiconductor memory device which can operate at high speed is obtained.Type: GrantFiled: June 7, 2006Date of Patent: March 24, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kiyoshi Kato, Atsuo Isobe, Hidekazu Miyairi, Shunpei Yamazaki
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Patent number: 7504327Abstract: In the invention, a low concentration impurity region is formed between a channel formation region and a source region or a drain region in a semiconductor layer and covered with a gate electrode layer in a thin film transistor The semiconductor layer is doped obliquely to the surface thereof using the gate electrode layer as a mask to form the low concentration impurity region. The semiconductor layer is formed to have an impurity region including an impurity element for imparting one conductivity which is different from conductivity of the thin film transistor, thereby being able to minutely control the properties of the thin film transistor.Type: GrantFiled: June 9, 2005Date of Patent: March 17, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Atsuo Isobe, Tetsuji Yamaguchi, Hiromichi Godo
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Patent number: 7504663Abstract: The present invention provides a semiconductor device capable of being mass-produced and a manufacturing method of the semiconductor device. The present invention also provides a semiconductor device using an extreme thin integrated circuit and a manufacturing method of the semiconductor device. Further, the present invention provides a low power consumption semiconductor device and a manufacturing method of the semiconductor device. According to one aspect of the present invention, a semiconductor device that has a semiconductor nonvolatile memory element transistor over an insulating surface in which a floating gate electrode of the memory transistor is formed by a plurality of conductive particles or semiconductor particles is provided.Type: GrantFiled: May 25, 2005Date of Patent: March 17, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Atsuo Isobe, Tetsuji Yamaguchi, Hiromichi Godo
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Patent number: 7501685Abstract: To provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a different layer from a gate electrode and the capacitor wiring is arranged so as to be parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of a neighboring pixel can be avoided, whereby obtaining satisfactory display images.Type: GrantFiled: March 29, 2005Date of Patent: March 10, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroshi Shibata, Atsuo Isobe
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Publication number: 20090029514Abstract: A method for manufacturing a semiconductor device, by which a bottom gate thin film transistor that has an improved S value and a channel forming region with a smaller thickness than that of a source region and a drain region can be manufactured in a simple process. An island-like conductive film is formed over a surface of an insulating substrate in a portion corresponding to a channel forming region, and is covered with an insulating film to form a projection portion. After an amorphous semiconductor film is deposited to cover the projection portion, the amorphous semiconductor film is irradiated with laser light so as to be melted and crystallized. Part of the melted semiconductor over the projection portion flows into regions adjacent to both sides of the projection portion, which results in reduction in thickness of the semiconductor film over the projection portion (channel forming region).Type: ApplicationFiled: July 23, 2008Publication date: January 29, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Tomokazu YOKOI, Atsuo ISOBE, Motomu KURATA, Takeshi SHICHI, Daisuke OHGARANE, Takashi SHINGU
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Publication number: 20090014799Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. A semiconductor device comprises a first single-crystal semiconductor layer including a first channel formation region and a first impurity region over a substrate having an insulating surface, a first gate insulating layer over the first single-crystal semiconductor layer, a gate electrode over the first gate insulating layer, a first interlayer insulating layer over the first gate insulating layer, a second gate insulating layer over the gate electrode and the first interlayer insulating layer, and a second single-crystal semiconductor layer including a second channel formation region and a second impurity region over the second gate insulating layer. The first channel formation region, the gate electrode, and the second channel formation region are overlapped with each other.Type: ApplicationFiled: July 8, 2008Publication date: January 15, 2009Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventor: Atsuo Isobe
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Publication number: 20090004822Abstract: A method of manufacturing a semiconductor substrate is demonstrated, which enables the formation of a single crystal semiconductor layer on a substrate having an insulating surface. The manufacturing method includes the steps of: ion irradiation of a surface of a single-crystal semiconductor substrate to form a damaged region; laser light irradiation of the single-crystal semiconductor substrate; formation of an insulating layer on the surface of the single-crystal semiconductor substrate; bonding the insulating layer with a substrate having an insulating surface; separation of the single-crystal semiconductor substrate at the damaged region, resulting in a thin single-crystal semiconductor layer on the surface of the substrate having the insulating surface; and laser light irradiation of the surface of the single-crystal semiconductor layer which is formed on the substrate having the insulating surface.Type: ApplicationFiled: June 13, 2008Publication date: January 1, 2009Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Murakami, Hiromichi Godo, Atsuo Isobe
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Patent number: 7465677Abstract: A manufacturing method of a semiconductor device of the present invention includes the steps of forming a first insulating film over a substrate, forming a semiconductor film over the first insulating film, oxidizing or nitriding the semiconductor film by conducting a plasma treatment to the semiconductor film under a condition of an electron density of 1×1011 cm?3 or more and 1×1013 cm?3 or less and an electron temperature of 0.5 eV or more and 1.5 eV or less, using a high frequency wave, forming a second insulating film to cover the semiconductor film, forming a gate electrode over the second insulating film, forming a third insulating film to cover the gate electrode, and forming a conductive film over the third insulating film.Type: GrantFiled: April 25, 2006Date of Patent: December 16, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Satoshi Murakami, Tamae Takano, Shunpei Yamazaki
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Patent number: 7449376Abstract: An object of the present invention is to form a channel formation region, or a TFT formation region, using one crystal aggregate (domain) by controlling crystal location and size, thus suppressing TFT variations. According to the present invention, laser irradiation is performed selectively on an amorphous silicon film in the periphery of a channel formation region, or the periphery of a TFT formation region containing a channel formation region, source and drain region, and the like. Each TFT formation region is isolated, a metallic element for promoting crystallization (typically Ni) is added, and heat treatment is performed, thus making it possible to arbitrarily determine the locations of crystal aggregates (domains). It becomes possible to suppress variations in the TFTs by arbitrarily controlling the crystal aggregate (domain) locations.Type: GrantFiled: May 4, 2005Date of Patent: November 11, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Tatsuya Arao
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Publication number: 20080272376Abstract: In a semiconductor device having a substrate which has a metal surface, an insulating film which is formed on the substrate having the metal surface, and a pixel unit which is formed on the insulating film; the pixel unit includes a TFT, and wiring lines connected with the TFT, and a storage capacitor is constituted by the substrate (11) having the metal surface, the insulating film (12), and the wiring line (21). As the insulating film is thinner, and as the area of a region where the insulating film and the wiring line lie in contact is larger, the storage capacitor is endowed with a larger capacity.Type: ApplicationFiled: July 10, 2008Publication date: November 6, 2008Inventors: Tatsuya Arao, Atsuo Isobe, Toru Takayama
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Publication number: 20080220570Abstract: A semiconductor device having a highly responsive thin film transistor (TFT) with low subthreshold swing and suppressed decrease in the on-state current and a manufacturing method thereof are demonstrated. The THF of the present invention is characterized by its semiconductor layer where the thickness of the source region or the drain region is larger than that of the channel formation region. Manufacture of the TFT is readily achieved by the formation of an amorphous semiconductor layer on a projection portion and a depression portion, which is followed by subjecting the melting process of the semiconductor layer, resulting in the formation of a crystalline semiconductor layer having different thicknesses. Selective addition of impurity to the thick portion of the semiconductor layer provides a semiconductor layer in which the channel formation region is thinner than the source or drain region.Type: ApplicationFiled: March 7, 2008Publication date: September 11, 2008Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Atsuo Isobe, Hiromichi Godo
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Patent number: 7410839Abstract: The present invention provides a thin film transistor in which a substantial length of a channel is shortened to miniaturize a semiconductor device and a manufacturing method thereof. In addition, the present invention provides a semiconductor device which realizes high-speed operation and high-performance of the semiconductor device and a manufacturing method thereof. Further in addition, it is an object of the present invention to provide a manufacturing method in which a manufacturing process is simplified. The semiconductor device of the present invention has an island-shaped semiconductor film formed over a substrate having an insulating surface and a gate electrode formed over the island-shaped semiconductor film, in which the gate electrode is oxidized its surface by high-density plasma to be slimmed and the substantial length of a channel is shortened.Type: GrantFiled: April 25, 2006Date of Patent: August 12, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Shunpei Yamazaki