Patents by Inventor Atsuo Isobe

Atsuo Isobe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080179675
    Abstract: A semiconductor device having a novel structure by which the operating characteristics and reliability are improved and a manufacturing method thereof. An island-shaped semiconductor layer provided over a substrate, including a channel formation region provided between a pair of impurity regions; a first insulating layer provided so as to be in contact with the side surface of the semiconductor layer; a gate electrode provided over the channel formation region so as to get across the semiconductor layer; and a second insulating layer provided between the channel formation region and the gate electrode are included. The semiconductor layer is locally thinned, the channel formation region is provided in the thinned region, and the second insulating layer covers the first insulating layer provided on the side surface of the semiconductor layer at least in the region which overlaps with the gate electrode.
    Type: Application
    Filed: January 16, 2008
    Publication date: July 31, 2008
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Atsuo ISOBE, Hiromichi GODO
  • Publication number: 20080179599
    Abstract: A salicide process is conducted to a thin film integrated circuit without worrying about damages to a glass substrate, and thus, high-speed operation of a circuit can be achieved. A base metal film, an oxide and a base insulating film are formed over a glass substrate. A TFT having a sidewall is formed over the base insulating film, and a metal film is formed to cover the TFT. Annealing is conducted by RTA or the like at such a temperature that does not cause shrinkage of the substrate, and a high-resistant metal silicide layer is formed in source and drain regions. After removing an unreacted metal film, laser irradiation is conducted for the second annealing; therefore a silicide reaction proceeds and the high-resistant metal silicide layer becomes a low-resistant metal silicide layer.
    Type: Application
    Filed: October 22, 2007
    Publication date: July 31, 2008
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuji YAMAGUCHI, Atsuo Isobe, Satoru Saito
  • Patent number: 7405132
    Abstract: In a semiconductor device having a substrate which has a metal surface, an insulating film which is formed on the substrate having the metal surface, and a pixel unit which is formed on the insulating film; the pixel unit includes a TFT, and wiring lines connected with the TFT, and a storage capacitor is constituted by the substrate (11) having the metal surface, the insulating film (12), and the wiring line (21). As the insulating film is thinner, and as the area of a region where the insulating film and the wiring line lie in contact is larger, the storage capacitor is endowed with a larger capacity.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: July 29, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Arao, Atsuo Isobe, Toru Takayama
  • Publication number: 20080142921
    Abstract: To fabricate a Schottky barrier diode in which a decrease in on current due to parasitic resistance is suppressed, variations in on current are suppressed, and an increase in off current is suppressed. The fabricating method includes the steps of forming an island-shape semiconductor film; doping the island-shape semiconductor film with a first impurity element to form a first impurity region; forming an insulating film so as to cover the island-shape semiconductor film; etching the insulating film to form a first opening and a second opening that partly expose the first impurity region; forming a mask over the insulating film so as to cover the first opening and expose the second opening; doping the first impurity region with a second impurity element to form a second impurity region; and forming a first wiring in contact with the first impurity region exposed at the first opening, and forming a second wiring in contact with the second impurity region exposed at the second opening.
    Type: Application
    Filed: December 13, 2007
    Publication date: June 19, 2008
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo ISOBE, Suguru OZAWA
  • Patent number: 7387922
    Abstract: In a laser irradiation system, since a heavy scanning stage moves at a high speed, vibration is caused. When the vibration is transmitted to a vibration isolator where an optical system that forms a beam spot and a system are mounted, a laser irradiation track formed on a substrate, which is not linear any more, is undulating in a reflection of the vibration. It is one of the objects of the present invention to suppress the undulation of the irradiation tracks due to such vibration. A light-shielding film 134 is provided over a semiconductor film 133 that is to be irradiated. When the light-shielding film 134 is provided, a portion of the incident beam, which has a low energy density, is shielded. As described above, providing the light-shielding film 134 makes it possible to enlarge a grain size in the semiconductor film without forming the state similar to the crystals formed in the case of performing laser crystallization with an excimer laser.
    Type: Grant
    Filed: January 2, 2004
    Date of Patent: June 17, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Atsuo Isobe, Tomoaki Moriwaka
  • Publication number: 20080138943
    Abstract: An object of the present invention is to provide a semiconductor device formed by laser crystallization by which formation of grain boundaries in the TFT channel formation region can be avoided, and a method of manufacturing the same. Still another object of the present invention is to provide a method of designating the semiconductor device.
    Type: Application
    Filed: January 4, 2008
    Publication date: June 12, 2008
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Toshihiko Saito, Atsuo Isobe, Toru Takayama, Junya Maruyama, Yuugo Goto, Yumiko Ohno
  • Patent number: 7371623
    Abstract: The invention is to provide a high-productivity method for fabricating a TFT device having different LDD structures on one and the same substrate, and the TFT device. Specifically, the invention provides a novel TFT structure, and a high-productivity method for fabricating it. A Ta film or a Ta-based film having good heat resistance is used for forming interconnections, and the interconnections are covered with a protective film. The interconnections can be subjected to heat treatment at high temperatures (400 to 700° C.), and, in addition, the protective film serves as an etching stopper. In the peripheral driving circuit portion in the device, TFTs having an LDD structure are disposed in a self-aligned process in which is used side walls 126 and 127; while in the pixel matrix portion therein, TFTs having an LDD structure are disposed in a non-self-aligned process in which is used an insulator 125.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: May 13, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Etsuko Fujimoto, Atsuo Isobe, Toru Takayama, Kunihiko Fukuchi
  • Patent number: 7365611
    Abstract: A test circuit and a test method using a plurality of oscillation circuits for evaluation are provided in order to reduce the measuring time and simplify the test. One measuring terminal is shared by a plurality of oscillation circuits for evaluation that are formed over the same substrate as a semiconductor device such as a display device, and the plurality of oscillation circuits for evaluation can be tested by the measuring output terminal. Then, the measurement results are Fourier transformed to obtain the oscillation frequency of the plurality of oscillation circuits for evaluation at the same time. Thus, variations in semiconductor elements can be evaluated.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: April 29, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Atsuo Isobe, Yoshiyuki Kurokawa
  • Publication number: 20080070352
    Abstract: An impurity of one conductivity type is ionized and accelerated by electric field before being implanted into a semiconductor layer to form a high concentration impurity region near its surface. Then the semiconductor layer is irradiated with continuous wave laser light for melting and crystallization or recrystallization, through which a region where the concentration of the impurity is constant is formed in the semiconductor layer. The continuous wave laser light irradiation may bring the semiconductor layer to the crystalline phase from the amorphous phase as long as the impurity element is re-distributed. The impurity is segregated through this process to newly create a high concentration region. However, this region is removed and no problem arises.
    Type: Application
    Filed: October 30, 2007
    Publication date: March 20, 2008
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Osamu Nakamura, Tatsuya Arao, Hidekazu Miyairi, Atsuo Isobe, Tamae Takano, Kouki Inoue
  • Patent number: 7344925
    Abstract: An object of the present invention is to provide a semiconductor device formed by laser crystallization by which formation of grain boundaries in the TFT channel formation region can be avoided, and a method of manufacturing the same. Still another object of the present invention is to provide a method of designating the semiconductor device.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: March 18, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Toshihiko Saito, Atsuo Isobe, Toru Takayama, Junya Maruyama, Yuugo Goto, Yumiko Ohno
  • Publication number: 20080036935
    Abstract: To provide a liquid crystal display device having high quality display with a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a layer that is different from a gate electrode so that the capacitor wiring is arranged in parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of adjacent pixels can be avoided, thereby obtaining satisfactory display images.
    Type: Application
    Filed: October 15, 2007
    Publication date: February 14, 2008
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hiroshi SHIBATA, Atsuo ISOBE
  • Patent number: 7329594
    Abstract: An impurity of one conductivity type is ionized and accelerated by electric field before being implanted into a semiconductor layer to form a high concentration impurity region near its surface. Then the semiconductor layer is irradiated with continuous wave laser light for melting and crystallization or recrystallization, through which a region where the concentration of the impurity is constant is formed in the semiconductor layer. The continuous wave laser light irradiation may bring the semiconductor layer to the crystalline phase from the amorphous phase as long as the impurity element is re-distributed. The impurity is segregated through this process to newly create a high concentration region. However, this region is removed and no problem arises.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: February 12, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Osamu Nakamura, Tatsuya Arao, Hidekazu Miyairi, Atsuo Isobe, Tamae Takano, Kouki Inoue
  • Patent number: 7326961
    Abstract: To provide devices relating to a manufacturing method for a semiconductor device using a laser crystallization method, which is capable of reducing a cost involved in a design change, preventing a grain boundary from developing in a channel formation region of a TFT, and preventing a remarkable reduction in mobility of the TFT, a decrease in an ON current, and an increase in an OFF current due to the grain boundary and to a semiconductor device formed by using the manufacturing method. In a semiconductor device according to the present invention, among a plurality of TFTs formed on a base film, some TFTs are electrically connected to form logic elements. The plurality of logic elements are used to form a circuit. The base film has a plurality of projective portions having a rectangular or stripe shape.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: February 5, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Atsuo Isobe, Tamae Takano, Hidekazu Miyairi
  • Patent number: 7312473
    Abstract: In display devices using thin film transistors, a graphoepitaxy is used for a semiconductor layer crystallizing process. Thus, a display device in which crystallinity is improved, a variation in characteristics of thin film transistors is reduced, display nonuniformity is less, and a display quality is superior is provided. Steps are formed on a substrate in advance and an amorphous silicon film is formed thereon, and then laser crystallization is conducted in a direction perpendicular to the steps.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: December 25, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Atsuo Isobe, Hiroshi Shibata, Shunpei Yamazaki
  • Publication number: 20070292997
    Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device, capable of keeping a peeling layer from being peeled from a substrate in the phase before the completion of a semiconductor element and peeling a semiconductor element rapidly. It is considered that a peeling layer tends to be peeled from a substrate because the stress is applied to a peeling layer due to the difference in thermal expansion coefficient between a substrate and a peeling layer, or because the volume of a peeling layer is reduced and thus the stress is applied thereto by crystallization of the peeling layer due to heat treatment. Therefore, according to one feature of the invention, the adhesion of a substrate and a peeling layer is enhanced by forming an insulating film (buffer film) for relieving the stress on the peeling layer between the substrate and the peeling layer before forming the peeling layer over the substrate.
    Type: Application
    Filed: August 9, 2007
    Publication date: December 20, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junya Maruyama, Atsuo Isobe, Susumu Okazaki, Koichiro Tanaka, Yoshiaki Yamamoto, Koji Dairiki, Tomoko Tamura
  • Publication number: 20070252179
    Abstract: A manufacturing method of a semiconductor device of the present invention includes the steps of forming a stacked body in which a semiconductor film, a gate insulating film, and a first conductive film are sequentially stacked over a substrate; selectively removing the stacked body to form a plurality of island-shaped stacked bodies; forming an insulating film to cover the plurality of island-shaped stacked bodies; removing a part of the insulating film to expose a surface of the first conductive film, such that a surface of the first conductive film almost coextensive with a height of the insulating film; forming a second conductive film over the first conductive film and a left part of the insulating film; forming a resist over the second conductive film; selectively removing the first conductive film and the second conductive film using the resist as a mask.
    Type: Application
    Filed: April 16, 2007
    Publication date: November 1, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Tamae Takano, Yasuyuki Arai, Fumiko Terasawa
  • Patent number: 7288480
    Abstract: A salicide process is conducted to a thin film integrated circuit without worrying about damages to a glass substrate, and thus, high-speed operation of a circuit can be achieved. A base metal film, an oxide and a base insulating film are formed over a glass substrate. A TFT having a sidewall is formed over the base insulating film, and a metal film is formed to cover the TFT. Annealing is conducted by RTA or the like at such a temperature that does not cause shrinkage of the substrate, and a high-resistant metal silicide layer is formed in source and drain regions. After removing an unreacted metal film, laser irradiation is conducted for the second annealing; therefore a silicide reaction proceeds and the high-resistant metal silicide layer becomes a low-resistant metal silicide layer.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: October 30, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuji Yamaguchi, Atsuo Isobe, Satoru Saito
  • Patent number: 7282737
    Abstract: To provide a liquid crystal display device having high quality display with a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a layer that is different from a gate electrode so that the capacitor wiring is arranged in parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of adjacent pixels can be avoided, thereby obtaining satisfactory display images.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: October 16, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroshi Shibata, Atsuo Isobe
  • Patent number: 7282380
    Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device, capable of keeping a peeling layer from being peeled from a substrate in the phase before the completion of a semiconductor element and peeling a semiconductor element rapidly. It is considered that a peeling layer tends to be peeled from a substrate because the stress is applied to a peeling layer due to the difference in thermal expansion coefficient between a substrate and a peeling layer, or because the volume of a peeling layer is reduced and thus the stress is applied thereto by crystallization of the peeling layer due to heat treatment. Therefore, according to one feature of the invention, the adhesion of a substrate and a peeling layer is enhanced by forming an insulating film (buffer film) for relieving the stress on the peeling layer between the substrate and the peeling layer before forming the peeling layer over the substrate.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: October 16, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junya Maruyama, Atsuo Isobe, Susumu Okazaki, Koichiro Tanaka, Yoshiaki Yamamoto, Koji Dairiki, Tomoko Tamura
  • Publication number: 20070141816
    Abstract: The objective of the invention is to provide a method of fabricating semiconductor device using a laser crystallization method capable of preventing a grain boundary from being formed on the channel-forming region of a TFT and preventing the mobility of the TFT from extremely deteriorating, on-current from decreasing, or off-current from increasing due to a grain boundary and a semiconductor device fabricated by the fabrication method. Striped (banded) or rectangular concave and convex portions are formed. Then, a semiconductor film formed on an insulating film is irradiated with a laser beam diagonally to the longitudinal direction of concave and convex portions on the insulating film.
    Type: Application
    Filed: February 9, 2007
    Publication date: June 21, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Atsuo Isobe, Tomoaki Moriwaka, Akihisa Shimomura