Patents by Inventor Atsushi Harikai

Atsushi Harikai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230420277
    Abstract: Disclosed is a recipe proposal device 10 including: an input section 11 for inputting a target information regarding a target shape of a substrate to be processed in a substrate processing apparatus; a recipe proposal section 12 that proposes a process recipe used in the substrate processing apparatus in order to form the target shape, based on the target information; a calculation section 13 that calculates a prediction information regarding a predicted shape when the substrate is processed in the substrate processing apparatus using the process recipe; and a display section 14 that displays the target information and the prediction information.
    Type: Application
    Filed: June 5, 2023
    Publication date: December 28, 2023
    Inventors: Akihiro ITOU, Hiroshi SHIROUZU, Atsushi HARIKAI
  • Patent number: 11830758
    Abstract: A plasma processing method including: a process of placing a work piece on a stage provided in a chamber, the work piece including a substrate and a holding member having an adhesive layer on a surface and holding the substrate via the adhesive layer, and having an exposed portion where the adhesive layer is exposed outside the substrate; and a plasma etching process of etching the substrate with a plasma generated in the chamber, with the exposed portion exposed to the plasma. In response to occurrence of an interruption in the plasma etching process, a cleaning process of exposing a surface of the substrate to a plasma containing an oxidizing gas is performed, and then the plasma etching process is resumed.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: November 28, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Akihiro Itou
  • Patent number: 11817323
    Abstract: An etching method including: a preparation step of preparing a resin layer and an electronic component supported thereby; and a resin etching step of etching the resin layer. The electronic component has a first surface covered with a protective film, a second surface opposite thereto, and a sidewall therebetween. The second surface is facing the resin layer. The resin layer is larger than the electronic component when seen from the first surface side. The resin etching step includes: a deposition step of depositing a first film, using a first plasma, on a surface of the protective film and a surface of the resin layer; and a removal step of removing, using a second plasma, the first film deposited on the resin layer and at least part of the resin layer. The deposition and removal steps are alternately repeated, with the protective film allowed to continue to exist.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: November 14, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Akihiro Itou
  • Patent number: 11688641
    Abstract: An element chip manufacturing method including: attaching a substrate via a die attach film (DAF) to a holding sheet; forming a protective film that covers the substrate; forming an opening in the protective film with a laser beam, to expose the substrate in the dicing region therefrom; exposing the substrate to a first plasma to etch the substrate exposed from the opening, so that a plurality of element chips are formed from the substrate and so that the DAF is exposed from the opening; exposing the substrate to a second plasma to etch the die attach film exposed from the opening, so that the DAF is split so as to correspond to the element chips; and detaching the element chips from the holding sheet, together with the split DAF. The DAF is larger than the substrate. The method includes irradiating the laser beam to the DAF protruding from the substrate.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: June 27, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidefumi Saeki, Hidehiko Karasaki, Shogo Okita, Atsushi Harikai, Akihiro Itou
  • Patent number: 11682575
    Abstract: A plasma processing apparatus for plasma processing a substrate held on a conveying carrier, the carrier including a holding sheet and a frame supporting an outer periphery of the holding sheet. The apparatus includes a controller that controls a plasma generator, an electrostatic adsorption mechanism, and a lifting system, to sequentially execute: an adsorption step allowing the substrate to be adsorbed electrostatically to a stage; an etching step of exposing the substrate adsorbed electrostatically to the stage to an etching plasma; a frame separation step of lifting the support, to separate the frame away from the stage, with at least part of the holding sheet kept in contact with the stage; a holding sheet separation step of separating the holding sheet away from the stage; and a static elimination step of exposing the substrate separated away from the stage to a static elimination plasma.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: June 20, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita
  • Publication number: 20230114557
    Abstract: A plasma processing apparatus including: a chamber; a plasma generation unit configured to generate a plasma in the chamber; a stage 111 for placing a conveying carrier 10, the stage provided in the chamber; a cover 124 for covering at least part of the conveying carrier placed on the stage; a relative position change unit capable of changing a relative distance between the cover 124 and the stage 111 to a first distance and to a second distance smaller than the first distance; a determination unit configured to determine a placed state of the conveying carrier 10; and a control unit. The determination unit determines the placed state of the conveying carrier while the distance between the cover 124 and the stage 111 is the first distance, and the plasma processing is performed while the distance between the cover 124 and the stage 111 is the second distance.
    Type: Application
    Filed: October 3, 2022
    Publication date: April 13, 2023
    Inventors: Atsushi HARIKAI, Shogo OKITA
  • Publication number: 20230102635
    Abstract: An electronic component cleaning method including: a preparation step of preparing an electronic component having a first surface covered with a protective film, a second surface opposite to the first surface, a sidewall between the first and second surfaces, and an adhering matter adhering to the sidewall; and a sidewall cleaning step of cleaning the sidewall. The sidewall cleaning step includes a deposition step of depositing a first film on the protective film and a surface of the adhering matter, using a first plasma, and a removal step of removing the first film deposited on the surface of the adhering matter, together with at least part of the adhering matter, using a second plasma. In the sidewall cleaning step, the deposition step and the removal step are alternately repeated a plurality of times, so as to allow the protective film to continue to exist.
    Type: Application
    Filed: December 4, 2020
    Publication date: March 30, 2023
    Inventors: Shogo OKITA, Akihiro ITOU, Atsushi HARIKAI
  • Patent number: 11551974
    Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: January 10, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidefumi Saeki, Atsushi Harikai, Shogo Okita
  • Publication number: 20220406660
    Abstract: An element chip manufacturing method includes a step of preparing a substrate including a semiconductor layer and a wiring layer formed on the semiconductor layer and having a plurality of element regions and a dicing region defining the element regions, a laser grooving step of irradiating a laser beam to the wiring layer at the dicing region, to form an aperture exposing the semiconductor layer, and an individualization step of etching the semiconductor layer exposed from the aperture, with plasma, to divide the substrate into a plurality of element chips. The laser grooving step including a step of irradiating a first laser beam, to form a first groove exposing the semiconductor layer in the dicing region, and a step of irradiating a second laser beam, with a beam center positioned outside a side wall of the first groove, to widen the first groove into the aperture.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 22, 2022
    Inventors: Shogo OKITA, Hidehiko KARASAKI, Hidefumi SAEKI, Atsushi HARIKAI
  • Publication number: 20220402072
    Abstract: An element chip manufacturing method includes a step of preparing a substrate including a semiconductor layer and a wiring layer formed on the semiconductor layer, the substrate having element regions and a dicing region defining the element regions, a laser grooving step of irradiating a laser beam to the wiring layer at the dicing region, to form an aperture exposing the semiconductor layer, and a step of etching the semiconductor layer exposed from the aperture, with plasma, to divide the substrate into a plurality of element chips. The laser grooving step includes a step of irradiating a first laser beam having a first pulse width, to remove the wiring layer in an edge portion of the dicing region, and a step of irradiating a second laser beam having a second pulse width which is longer than the first pulse width, to remove the wiring layer inside from the edge portion.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 22, 2022
    Inventors: Hidefumi SAEKI, Hidehiko KARASAKI, Shogo OKITA, Atsushi HARIKAI, Akihiro ITOU
  • Publication number: 20220199411
    Abstract: Disclosed is a method for producing element chips. The method includes: a preparing step of preparing a substrate 10 that is held on a holding sheet 22 that is supported by a frame 21, the substrate including element regions and dicing regions; a protective film forming step of forming a protective film 15 so as to cover the frame 21, the holding sheet 22, and the substrate 10; a patterning step of removing a part of the protective film 15 so as to expose the dicing regions of the substrate 10; a plasma dicing step including a process that uses a plasma that contains fluorine, the plasma dicing step being a step of individualizing the substrate 10 into a plurality of element chips; and a fluorine removing step of removing, together with the protective film 15, fluorine attached to the protective film 15 in the plasma dicing step.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 23, 2022
    Inventors: Toshiyuki TAKASAKI, Ryota FURUKAWA, Atsushi HARIKAI, Shogo OKITA
  • Patent number: 11361944
    Abstract: A plasma processing method, including: a trenched substrate preparation process of preparing a trenched substrate having trenches having a bottom exposing an oxide film; and an oxide film removal process of exposing the trenched substrate to a plasma, to remove the oxide film. The oxide film removal process includes a plurality of cycles, each cycle including: an oxide film etching step of etching the oxide film; and a cleaning step of removing an attached matter on inner walls of the trenches, after the oxide film etching step.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: June 14, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita
  • Publication number: 20220181188
    Abstract: A plasma processing method including: a process of placing a work piece on a stage provided in a chamber, the work piece including a substrate and a holding member having an adhesive layer on a surface and holding the substrate via the adhesive layer, and having an exposed portion where the adhesive layer is exposed outside the substrate; and a plasma etching process of etching the substrate with a plasma generated in the chamber, with the exposed portion exposed to the plasma. In response to occurrence of an interruption in the plasma etching process, a cleaning process of exposing a surface of the substrate to a plasma containing an oxidizing gas is performed, and then the plasma etching process is resumed.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 9, 2022
    Inventors: Atsushi Harikai, Shogo Okita, Akihiro Itou
  • Publication number: 20220181209
    Abstract: The element chip manufacturing method includes: a preparing process of preparing a substrate 1 including a plurality of element regions EA and a dividing region DA, the substrate 1 having a first principal surface 1X and a second principal surface 1Y; a groove forming process of forming a groove 13 in the dividing region DA from the first principal surface 1X side; and a grinding process of grinding the substrate 1 from the second principal surface 1Y side, to divide the substrate 1 into a plurality of element chips 20. The groove 13 includes a first region 13a constituted by a side surface having a first surface roughness, and a second region 13b constituted by a side surface having a second surface roughness larger than the first surface roughness. In the grinding process, grinding of the substrate 1 is performed until reaching the first region 13a of the groove 13.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 9, 2022
    Inventors: Atsushi HARIKAI, Shogo OKITA, Akihiro ITOU, Toshiyuki TAKASAKI
  • Publication number: 20220165577
    Abstract: A plasma processing method including: exposing to a first plasma a substrate having a compound semiconductor layer and a mask partially covering a surface of the compound semiconductor layer, to form a protective film at least on the bottom of a groove formed in a region where the compound semiconductor layer is not covered with the mask; removing the protective film at the bottom by exposing the substrate to a second plasma, to expose the compound semiconductor layer; and removing the conductive semiconductor layer exposed at the bottom of the groove by exposing the substrate to a third plasma generated from a gas containing chlorine and/or bromine, while allowing a reaction product between the compound semiconductor layer and the third plasma to accumulate on an upper portion of the groove. The reaction product is removed by applying a high-frequency power to a stage on which the substrate is placed.
    Type: Application
    Filed: November 19, 2021
    Publication date: May 26, 2022
    Inventors: Toshiyuki TAKASAKI, Shogo OKITA, Akihiro ITOU, Atsushi HARIKAI
  • Patent number: 11335564
    Abstract: An element chip smoothing method including: an element chip preparation step of preparing at least one element chip including a first surface covered with a resin film, a second surface opposite the first surface, and a sidewall connecting the first surface to the second surface and having ruggedness; a sidewall cleaning step of exposing the element chip to a first plasma, to remove deposits adhering to the sidewall, with the resin film allowed to continue to exist; a sidewall oxidation step of exposing the element chip to a second plasma, after the sidewall cleaning step, to oxidize a surface of the sidewall, with the resin film allowed to continue to exist; and a sidewall etching step of exposing the element chip to a third plasma, after the sidewall oxidation step, to etch the sidewall, with the resin film allowed to continue to exist.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: May 17, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akihiro Itou, Atsushi Harikai, Toshiyuki Takasaki, Shogo Okita
  • Patent number: 11219929
    Abstract: An element chip cleaning method including: an element chip preparation step of preparing at least one element chip having a first surface and a second surface opposite the first surface, the first surface covered with a resin film; a first cleaning step of bringing a first cleaning liquid into contact with the resin film, the first cleaning liquid including a solvent that dissolves at least part of a resin component contained in the resin film; and a second cleaning step of spraying a second cleaning liquid against the resin film from the first surface side of the element chip, after the first cleaning step.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: January 11, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akihiro Itou, Atsushi Harikai, Toshiyuki Takasaki, Hidefumi Saeki, Shogo Okita
  • Publication number: 20210407855
    Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.
    Type: Application
    Filed: September 10, 2021
    Publication date: December 30, 2021
    Inventors: Hidefumi SAEKI, Atsushi HARIKAI, Shogo OKITA
  • Patent number: 11189480
    Abstract: An element chip manufacturing method including: a preparing step of preparing a substrate including a plurality of element regions and a dicing region defining the element regions, the substrate having a first surface and a second surface opposite the first surface; a laser scribing step of applying a laser beam to the dicing region from a side of the first surface, to form a groove corresponding to the dicing region and being shallower than a thickness of the substrate; a cleaning step of exposing the first surface of the substrate to a first plasma, to remove debris on the groove; and a dicing step of exposing the substrate at a bottom of the groove to a second plasma after the cleaning step, to dice the substrate into element chips including the element regions. The first plasma is generated from a process gas containing a carbon oxide gas.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: November 30, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Akihiro Itou
  • Patent number: 11145548
    Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: October 12, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidefumi Saeki, Atsushi Harikai, Shogo Okita