Patents by Inventor Atsushi Harikai

Atsushi Harikai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10037891
    Abstract: A manufacturing method of an element chip includes a preparation process of adhering a holding sheet to the first main surface of a substrate so as to prepare the substrate held by the holding sheet, a plasma dicing process of performing plasma etching on the isolation region of the substrate to the first main surface so as to divide the substrate into the plurality of element chips. The plasma dicing process includes a first plasma etching process of performing plasma etching on a the isolation region partially in a thickness direction while a cooling gas is supplied between the stage and the holding sheet, and a second plasma etching process of stopping a supply of the cooling gas after the first plasma etching process, and performing plasma etching on a remaining portion of the isolation region.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: July 31, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai
  • Patent number: 10026619
    Abstract: The yield of a product is improved when a substrate held by a conveyance carrier is subjected to a plasma treatment. A plasma treatment method of the substrate held by the conveyance carrier includes preparing the conveyance carrier which includes a holding sheet and a frame disposed on the outer peripheral portion of the holding sheet; bonding the substrate to the holding sheet so that the substrate is held by the conveyance carrier; and increasing tensile strength of the holding sheet. The plasma treatment method further includes placing the conveyance carrier on the stage after the bonding of the substrate and bringing the substrate into contact with the stage through the holding sheet; and performing a plasma treatment on the substrate after the placing of the conveyance carrier.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: July 17, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai
  • Publication number: 20180197777
    Abstract: Provided is a manufacturing process of an element chip, which comprises a preparation step for preparing a substrate including a semiconductor layer having first and second sides and a wiring layer on the first side thereof, the substrate having a plurality of dicing regions and element regions defined by the dicing regions, a scribing step for radiating a laser beam towards the first side of the wiring layer onto the dicing regions to form apertures exposing the semiconductor layer along the dicing regions, and a dicing step for dicing the substrate along the apertures into a plurality of the element chips, wherein the laser beam has a beam profile having a M-shaped distribution whose peripheral intensity is greater than a central intensity in a width direction of the laser beam along the dicing regions.
    Type: Application
    Filed: January 3, 2018
    Publication date: July 12, 2018
    Inventors: Hidehiko KARASAKI, Hidefumi SAEKI, Atsushi HARIKAI
  • Publication number: 20180174908
    Abstract: A manufacturing process of an element chip comprises a preparation step for preparing a substrate, the substrate including first and second streets crossing each other to define a plurality of element regions. Also, it comprises a first shallow-groove formation step for radiating a laser beam along the first streets to form a plurality of first shallow grooves being shallower than a thickness of the substrate, a second shallow-groove formation step for radiating the laser beam along the second streets to form a plurality of second shallow grooves being shallower than a thickness of the substrate, a first groove formation step for radiating the laser beam along the first shallow grooves to form a plurality of first grooves, and a plasma dicing step for etching the substrate along the first grooves and the second shallow grooves by a plasma exposure to dice the substrate into a plurality of element chips.
    Type: Application
    Filed: November 14, 2017
    Publication date: June 21, 2018
    Inventors: Hidehiko KARASAKI, Hidefumi SAEKI, Atsushi HARIKAI
  • Publication number: 20180158713
    Abstract: Provided is a method of manufacturing a semiconductor chip, the method comprising: preparing a plurality of semiconductor chips, each of which has a surface to which a BG tape is stuck, and a rear surface to which a DAF is stuck, and which are held spaced from each other by the BG tape and the DAF, exposing the DAF between semiconductor chips that are adjacent to each other when viewed from the surface side, by stripping the BG tape from the surface of each of the plurality of semiconductor chips, etching the DAF that is exposed between the semiconductor chips that are adjacent to each other, by irradiating the plurality of semiconductor chips held on the DAF, with plasma.
    Type: Application
    Filed: November 27, 2017
    Publication date: June 7, 2018
    Inventors: SHOGO OKITA, ATSUSHI HARIKAI, NORIYUKI MATSUBARA, AKIHIRO ITOU
  • Patent number: 9953906
    Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by insulating film, the substrate is divided into element chips by exposing the substrate to a first plasma, element chips having first surface, second surface, and side surface are held spaced from each other on carrier, insulating film is in a state of being exposed, recessed portions are formed by retreating insulating film by exposing element chips to second plasma for ashing, and then recessed portions are covered by protection films by third plasma for formation of the protection film, thereby suppressing creep-up of the conductive material to side surface in the mounting step.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: April 24, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara
  • Patent number: 9941132
    Abstract: A plasma processing apparatus includes: a reaction chamber; a plasma generation unit; a stage disposed inside the reaction chamber; an electrostatic chuck mechanism including an electrode portion inside the stage; a heater inside the stage; a support portion which supports a conveyance carrier between a stage-mounted position on the stage and a transfer position distant from the stage upward; and an elevation mechanism which elevates and lowers the support portion relative to the stage. In a case in which the conveyance carrier is mounted on the stage by lowering the support portion, application of voltage to the electrode portion is started in a state that the stage is being heated, and the plasma generation unit generates plasma after at least a part of an outer circumferential portion of a holding sheet holding the conveyance carrier contacts the stage and also after the heating of the stage is stopped.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: April 10, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Noriyuki Matsubara
  • Patent number: 9922899
    Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into the element chips by exposing the substrate to first plasma. Therefore, the element chips having a first surface, a second surface, and a side surface on which a plurality of convex portions are formed are held spaced from each other on a carrier. A protection film is formed on the side surface of the element chip by exposing the element chip to second plasma, at least convex portions formed on the side surface are covered by the protection film in the protection film formation, and creep-up of a conductive material to the side surface is suppressed in the mounting step.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: March 20, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara, Mitsuru Hiroshima, Mitsuhiro Okune
  • Patent number: 9911677
    Abstract: A method for manufacturing an element chip includes a protection film etching step of removing a part of the protection film which is stacked on the dividing region and the protection film which is stacked on the element region through etching the protection film anisotropically by exposing the substrate to first plasma and remaining the protection film for covering an end surface of the element region. Furthermore, the method for manufacturing an element chip includes an isotropic etching step of etching the dividing region isotropically by exposing the substrate to second plasma and a plasma dicing step of dividing the substrate to a plurality of element chips including the element region by exposing the substrate to third plasma in a state where the second main surface is supported by a supporting member.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: March 6, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Bunzi Mizuno, Mitsuru Hiroshima, Shogo Okita, Noriyuki Matsubara, Atsushi Harikai
  • Patent number: 9911638
    Abstract: A plasma processing apparatus includes: a reaction chamber; a plasma generation unit; a stage disposed inside the reaction chamber; an electrostatic chuck mechanism including an electrode portion disposed inside the stage; a support portion which supports the conveyance carrier; and an elevation mechanism which elevates and lowers the support portion relative to the stage. In a case in which the conveyance carrier is mounted on the stage, the electrostatic chuck mechanism performs an operation of applying a voltage to the electrode portion after contact of an outer circumferential portion of a holding sheet of the conveyance carrier to the stage, the operation including a voltage varying operation of increasing and decreasing an absolute value of the voltage, and the plasma generation unit generates plasma after completion of the voltage varying operation.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: March 6, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Noriyuki Matsubara
  • Patent number: 9905452
    Abstract: In a method of fabricating element chips, a method of forming a mask pattern, and a method of processing a substrate, a process sequence is set such that developing in which the exposure-ended protection film is patterned is performed, after grinding in which the substrate is thinned by grinding a second surface opposite to a first surface to which a photosensitive protection film is pasted. Thereby, it is possible to perform the grinding for thinning in a state where the protection film is stable without being patterned, and to prevent the substrate or the protection film on which a mask pattern of the substrate is formed from being damaged at the time of the grinding, even in a case where a thin substrate of a wafer shape becomes a target.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: February 27, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Mitsuru Hiroshima, Atsushi Harikai
  • Publication number: 20180012802
    Abstract: A semiconductor chip manufacturing method includes preparing a semiconductor wafer including a front surface on which a bump is exposed, a rear surface located at a side opposite to the front surface, a plurality of element regions in each of which the bump is formed, and a dividing region defining each of the element regions, forming a mask which covers the bump and has an opening exposing the dividing region on the surface of the semiconductor wafer by spraying liquid which contains raw material of the mask along the bump by a spray coating method, and singulating the semiconductor wafer by exposing the surface of the semiconductor wafer to first plasma and etching the dividing region, which is exposed to the opening, until the rear surface is reached in a state where the bump is covered by the mask.
    Type: Application
    Filed: June 14, 2017
    Publication date: January 11, 2018
    Inventors: SHOGO OKITA, MITSURU HIROSHIMA, ATSUSHI HARIKAI, NORIYUKI MATSUBARA, AKIHIRO ITOU
  • Patent number: 9859144
    Abstract: In a plasma processing process used for a method of manufacturing element chips by which a plurality of element chips are manufactured by dividing a substrate having a plurality of element regions, the substrate is exposed to first plasma, and thereby the substrate is divided into element chips, and the element chips having first surfaces, second surfaces, and side surfaces connecting the first surfaces to the second surfaces are held with an interval between the element chips on the carrier. The element chips are exposed to second plasma which uses a mixed gas of fluorocarbon and helium as a raw material gas, and thereby a protection film covering the side surfaces is formed, and a conductive material is prevented from creeping up to the side surfaces during a mounting process.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: January 2, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara
  • Publication number: 20170345781
    Abstract: An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface having an exposed bump and a second surface opposite to the first surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of embedding at least a head top part of the bump into the adhesive layer, a mask forming process of forming a mask in the second surface. The method for manufacturing the element chip includes a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape, a placement process of placing the substrate on a stage provided inside of a plasma processing apparatus through the holding tape, after the mask forming process and the holding process.
    Type: Application
    Filed: May 15, 2017
    Publication date: November 30, 2017
    Inventors: ATSUSHI HARIKAI, SHOGO OKITA, AKIHIRO ITOU, KATSUMI TAKANO, MITSURU HIROSHIMA
  • Publication number: 20170345715
    Abstract: An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface provided with a bump and a second surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of adhering a protection tape having an adhesive layer to the first surface and embedding. The element chip manufacturing method includes a thinning process of grinding the second surface in a state where the protection tape is adhered to the first surface and thinning the substrate, after the bump embedding process, a mask forming process of forming a mask in the second surface and exposes the dividing regions, after the thinning process, a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape.
    Type: Application
    Filed: May 15, 2017
    Publication date: November 30, 2017
    Inventors: ATSUSHI HARIKAI, SHOGO OKITA, AKIHIRO ITOU, KATSUMI TAKANO, MITSURU HIROSHIMA
  • Patent number: 9780021
    Abstract: To provide a method of manufacturing an element chip in which creep-up of a conductive material can be suppressed in a mounting step. In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by an insulating film, the substrate is divided into the element chips by exposing the substrate to a first plasma, the element chips having a first surface, a second surface, and a side surface are held spaced from each other on a carrier, and the side surface and the insulating film are in a state of being exposed.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: October 3, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara
  • Patent number: 9779986
    Abstract: Provided is a plasma treatment method including: placing a substrate carrier holding a substrate on a stage; adjusting a distance between a cover and the stage to a first distance in which the cover covers a frame without coming into contact with the substrate carrier; performing a plasma treatment on the substrate placed on the stage after the adjusting of the distance; carrying the substrate together with the substrate carrier out from a reaction chamber after the performing of the plasma treatment; and removing an adhered substance adhered to the cover by generating plasma in the inside of the reaction chamber after the carrying of the substrate, in which the distance between the cover and the stage in the removing of the adhered substance is a second distance greater than the first distance.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: October 3, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Noriyuki Matsubara, Hideo Kanou, Mitsuru Hiroshima, Syouzou Watanabe, Toshihiro Wada
  • Publication number: 20170271194
    Abstract: A plasma processing method includes a mounting process of mounting a holding sheet holding a substrate in a stage provided in a plasma processing apparatus, and a fixing process of fixing the holding sheet to the stage. The plasma processing method further includes a determining process of determining whether or not a contact state of the holding sheet with the stage is good or bad after the fixing process, and a plasma etching process of etching the substrate by exposing a surface of the substrate to plasma on the stage, in a case in which the contact state is determined to be good in the determining process.
    Type: Application
    Filed: February 8, 2017
    Publication date: September 21, 2017
    Inventors: SHOGO OKITA, ATSUSHI HARIKAI, AKIHIRO ITOU
  • Publication number: 20170263526
    Abstract: A method for manufacturing an element chip includes a protection film etching step of removing a part of the protection film which is stacked on the dividing region and the protection film which is stacked on the element region through etching the protection film anisotropically by exposing the substrate to first plasma and remaining the protection film for covering an end surface of the element region. Furthermore, the method for manufacturing an element chip includes an isotropic etching step of etching the dividing region isotropically by exposing the substrate to second plasma and a plasma dicing step of dividing the substrate to a plurality of element chips including the element region by exposing the substrate to third plasma in a state where the second main surface is supported by a supporting member.
    Type: Application
    Filed: February 8, 2017
    Publication date: September 14, 2017
    Inventors: BUNZI MIZUNO, MITSURU HIROSHIMA, SHOGO OKITA, NORIYUKI MATSUBARA, ATSUSHI HARIKAI
  • Publication number: 20170263462
    Abstract: A manufacturing method of an element chip includes a preparation process of adhering a holding sheet to the first main surface of a substrate so as to prepare the substrate held by the holding sheet, a plasma dicing process of performing plasma etching on the isolation region of the substrate to the first main surface so as to divide the substrate into the plurality of element chips. The plasma dicing process includes a first plasma etching process of performing plasma etching on a the isolation region partially in a thickness direction while a cooling gas is supplied between the stage and the holding sheet, and a second plasma etching process of stopping a supply of the cooling gas after the first plasma etching process, and performing plasma etching on a remaining portion of the isolation region.
    Type: Application
    Filed: February 8, 2017
    Publication date: September 14, 2017
    Inventors: SHOGO OKITA, ATSUSHI HARIKAI