Patents by Inventor Atsushi Hiraishi

Atsushi Hiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8680174
    Abstract: The present invention is directed to a water dispersion for ink-jet printing which realizes sufficient optical density and exhibits excellent filterability and storage stability; a water-based ink containing the water dispersion; and a process for producing the water dispersion or the water-based ink.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: March 25, 2014
    Assignee: Kao Corporation
    Inventors: Atsushi Hiraishi, Kyoichi Shirota, Yuki Wakabayashi, Yasuhiro Doi
  • Publication number: 20140001639
    Abstract: Disclosed herein is a device that includes a silicon interposer having wiring lines on first and second wiring layers. The wiring lines includes first, second and third wiring lines provided on the first wiring layer and a fourth wiring line provided on the second wiring layer. The third wiring line is arranged between the first and second wiring lines on the first wiring layer. The fourth wiring line is overlapped with the third wiring line. Each of the first, second and fourth wiring lines conveys a power supply potential to first and second semiconductor chips mounted on the silicon interposer, and the third wiring line conveys a first signal communicated between the first and second semiconductor chips.
    Type: Application
    Filed: June 25, 2013
    Publication date: January 2, 2014
    Applicant: Elpida Memory, Inc.
    Inventors: Atsushi HIRAISHI, Toshio SUGANO, Yasuhiro TAKAI
  • Patent number: 8422263
    Abstract: A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: April 16, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi, Fumiyuki Osanai, Masayuki Nakamura, Hiroki Fujisawa
  • Patent number: 8394871
    Abstract: The present invention provides [1] a water dispersion for ink-jet printing containing chain-like particles each containing anionic organic pigment particles and a cationic polymer, wherein the ratio of organic pigment primary particles forming the chain-like particles to all the pigment primary particles contained in the water dispersion is 10% by number or more; [2] a water-based ink for ink-jet printing containing the water dispersion; [3] a method for producing a water dispersion for ink-jet printing as described above in [1]; and [4] a water-based ink for ink-jet printing containing a water dispersion produced through the method. The water dispersion and water-based ink for ink-jet printing of the present invention realize excellent optical density.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: March 12, 2013
    Assignee: KAO Corporation
    Inventors: Atsushi Hiraishi, Masayuki Narita, Takahiro Sato, Kyoichi Shirota, Yasuhiro Doi, Hiroyuki Yoshida, Yusuke Shimizu
  • Patent number: 8198549
    Abstract: A multi-layer printed circuit board for mounting memories, includes: laminated wiring layers on which wiring is arranged; and a plurality of interlayer connection components which electrically connect at least two of the wiring layers. At least one of the plurality of interlayer connection components is a blind via-hole.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: June 12, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi
  • Publication number: 20120127675
    Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.
    Type: Application
    Filed: February 1, 2012
    Publication date: May 24, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventors: ATSUSHI HIRAISHI, TOSHIO SUGANO, MASAHIRO YAMAGUCHI, YOJI NISHIO, TSUTOMU HARA, KOICHIRO AOKI
  • Patent number: 8134239
    Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: March 13, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Atsushi Hiraishi, Toshio Sugano, Masahiro Yamaguchi, Yoji Nishio, Tsutomu Hara, Koichiro Aoki
  • Publication number: 20110306708
    Abstract: The present invention is directed to a water dispersion for ink-jet printing which realizes sufficient optical density and exhibits excellent filterability and storage stability; a water-based ink containing the water dispersion; and a process for producing the water dispersion or the water-based ink.
    Type: Application
    Filed: December 11, 2009
    Publication date: December 15, 2011
    Applicant: KAO CORPORATION
    Inventors: Atsushi Hiraishi, Kyoichi Shirota, Yuki Wakabayashi, Yasuhiro Doi
  • Patent number: 8064236
    Abstract: In a multi-rank memory module having a terminal resistance of a data input/output pad 13 and a terminal resistance control pad 14 that inputs a signal that controls on/off of the terminal resistance, a high-speed operation is enabled with the aid of an enclosed terminal resistance, even in cases where the number of ranks is greater than that of terminal resistance control terminals (ODT terminals) provided on the memory module. To this end, a terminal resistance control pad 14 of a memory chip 12, having a longer length of an interconnect between a data bus 19 on a module substrate 8 and a data input/output pad 13, is connected to a terminal resistance control interconnect 18 or 21 to control the on/off of the terminal resistance from the ODT terminal. A terminal resistance control pad on a memory chip 11, having a shorter length of an interconnect between the data bus 19 on the module substrate and the data input/output pad 13, is connected to a fixed potential 20 to turn on the terminal resistance.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: November 22, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Yoji Nishio, Atsushi Hiraishi
  • Publication number: 20110263752
    Abstract: The present invention provides [1] a water dispersion for ink-jet printing containing chain-like particles each containing anionic organic pigment particles and a cationic polymer, wherein the ratio of organic pigment primary particles forming the chain-like particles to all the pigment primary particles contained in the water dispersion is 10% by number or more; [2] a water-based ink for ink-jet printing containing the water dispersion; [3] a method for producing a water dispersion for ink-jet printing as described above in [1]; and [4] a water-based ink for ink-jet printing containing a water dispersion produced through the method. The water dispersion and water-based ink for ink-jet printing of the present invention realize excellent optical density.
    Type: Application
    Filed: November 20, 2009
    Publication date: October 27, 2011
    Applicant: KAO CORPORATION
    Inventors: Atsushi Hiraishi, Masayuki Narita, Takahiro Sato, Kyoichi Shirota, Yasuhiro Doi, Hiroyuki Yoshida, Yusuke Shimizu
  • Publication number: 20100312925
    Abstract: A memory module includes a plurality of data connectors provided along a long side of a module substrate, a plurality of memory chips and a plurality of data register buffers mounted on the module substrate, a data line that connects the data connectors and the data register buffers, and data lines that connect the data register buffers and the memory chips. Each of the data register buffers and a plurality of data connectors and a plurality of memory chips corresponding to the data register buffer are arranged side by side in a direction of a short side of the module substrate. According to the present invention, because each line length of the data lines is considerably shortened, it is possible to realize a considerably high data transfer rate.
    Type: Application
    Filed: June 3, 2010
    Publication date: December 9, 2010
    Applicant: Elpida Memory, Inc.
    Inventors: Fumiyuki Osanai, Toshio Sugano, Atsushi Hiraishi, Shunichi Saito, Masayuki Nakamura, Hiroki Fujisawa
  • Publication number: 20100309706
    Abstract: A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.
    Type: Application
    Filed: June 3, 2010
    Publication date: December 9, 2010
    Applicant: Elpida Memory, Inc.
    Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi, Fumiyuki Osanai, Masayuki Nakamura, Hiroki Fujisawa
  • Publication number: 20100312956
    Abstract: A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register buffers. Each of the data register buffers includes M input/output terminals (M is a positive integer equal to or larger than 1) that are connected to the data connectors via a first data line and N input/output terminals (N is a positive integer equal to or larger than 2M) that are connected to corresponding memory chips via second and third data lines, so that the number of the second and third data lines is N/M times the number of the first data lines. According to the present invention, because the load capacities of the second and third data lines are reduced by a considerable amount, it is possible to realize a considerably high data transfer rate.
    Type: Application
    Filed: June 3, 2010
    Publication date: December 9, 2010
    Applicant: Elpida Memory, Inc.
    Inventors: Atsushi Hiraishi, Toshio Sugano, Fumiyuki Osanai, Masayuki Nakamura, Hiroki Fujisawa, Shunichi Saito
  • Patent number: 7777517
    Abstract: A signal transmission circuit comprising: first and second transmission lines connected to each other; a first impedance storage circuit storing an impedance of the first transmission line; and a control circuit that outputs match information between an impedance of the second transmission line and the impedance stored in the first impedance storage circuit.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: August 17, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Atsushi Hiraishi, Toshio Sugano
  • Patent number: 7740742
    Abstract: The powder composition for paper manufacturing of the invention contains a hydrophobic organic compound (A), an emulsifying and dispersing agent (B), and optionally water-soluble saccharides (C) added based on necessity and has an average particle diameter of 0.1 to 2,000 ?m.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: June 22, 2010
    Assignee: Kao Corporation
    Inventors: Yoshihito Hamada, Kazuo Kubota, Atsushi Hiraishi, Jun Kozuka, Takahiro Kawaguchi, Tsutomu Miyahara, Hiroshi Noro, Koichi Ohori, Haruyuki Sato
  • Patent number: 7714424
    Abstract: Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tape. An electric length of the second signal transmission path is allowed to be adjusted independently of the first tape, so that the electric length of the second signal transmission path can be easily made equal to or substantially equal to that of the first signal transmission path.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: May 11, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Mitsuaki Katagiri, Atsushi Hiraishi, Fumiyuki Osanai
  • Patent number: 7667317
    Abstract: A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: February 23, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Fumiyuki Osanai, Atsushi Hiraishi, Toshio Sugano, Tsuyoshi Tomoyama, Satoshi Isa, Masahiro Yamaguchi, Masanori Shibamoto
  • Publication number: 20090303768
    Abstract: In a multi-rank memory module having a terminal resistance of a data input/output pad 13 and a terminal resistance control pad 14 that inputs a signal that controls on/off of the terminal resistance, a high-speed operation is enabled with the aid of an enclosed terminal resistance, even in cases where the number of ranks is greater than that of terminal resistance control terminals (ODT terminals) provided on the memory module. To this end, a terminal resistance control pad 14 of a memory chip 12, having a longer length of an interconnect between a data bus 19 on a module substrate 8 and a data input/output pad 13, is connected to a terminal resistance control interconnect 18 or 21 to control the on/off of the terminal resistance from the ODT terminal. A terminal resistance control pad on a memory chip 11, having a shorter length of an interconnect between the data bus 19 on the module substrate and the data input/output pad 13, is connected to a fixed potential 20 to turn on the terminal resistance.
    Type: Application
    Filed: June 3, 2009
    Publication date: December 10, 2009
    Applicant: Elpida Memory, Inc.
    Inventors: Yoji NISHIO, Atsushi Hiraishi
  • Publication number: 20090140766
    Abstract: A signal transmission circuit comprising: first and second transmission lines connected to each other; a first impedance storage circuit storing an impedance of the first transmission line; and a control circuit that outputs match information between an impedance of the second transmission line and the impedance stored in the first impedance storage circuit.
    Type: Application
    Filed: November 24, 2008
    Publication date: June 4, 2009
    Applicant: Elpida Memory, Inc.
    Inventors: Atsushi Hiraishi, Toshio Sugano
  • Publication number: 20090086522
    Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.
    Type: Application
    Filed: September 29, 2008
    Publication date: April 2, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Atsushi HIRAISHI, Toshio Sugano, Masahiro Yamaguchi, Yoji Nishio, Tsutomu Hara, Koichiro Aoki