Patents by Inventor Atsushi Hiraishi
Atsushi Hiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9805786Abstract: Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.Type: GrantFiled: January 6, 2017Date of Patent: October 31, 2017Assignee: Micron Technology, Inc.Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi, Atsuo Koshizuka
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Patent number: 9570375Abstract: Disclosed herein is a device that includes a silicon interposer having wiring lines on first and second wiring layers. The wiring lines includes first, second and third wiring lines provided on the first wiring layer and a fourth wiring line provided on the second wiring layer. The third wiring line is arranged between the first and second wiring lines on the first wiring layer. The fourth wiring line is overlapped with the third wiring line. Each of the first, second and fourth wiring lines conveys a power supply potential to first and second semiconductor chips mounted on the silicon interposer, and the third wiring line conveys a first signal communicated between the first and second semiconductor chips.Type: GrantFiled: June 25, 2013Date of Patent: February 14, 2017Assignee: Longitude Semiconductor S.a.r.l.Inventors: Atsushi Hiraishi, Toshio Sugano, Yasuhiro Takai
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Publication number: 20160267962Abstract: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.Type: ApplicationFiled: May 19, 2016Publication date: September 15, 2016Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi
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Patent number: 9368185Abstract: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.Type: GrantFiled: October 7, 2014Date of Patent: June 14, 2016Assignee: Micron Technology, Inc.Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi
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Patent number: 9076500Abstract: Disclosed herein is a memory module that includes a module substrate, data connectors, memory devices, and data register buffers. A first main surface of the module substrate has first and second memory mounting areas. One of the first and second main surfaces of the module substrate has a register mounting area located between the first and second memory mounting areas in a planner view. The memory devices include a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area. The data register buffers are mounted on the register mounting area. The data register buffers transfers write data supplied from the data connectors to the memory devices, and transfers read data supplied from the memory devices to the data connectors.Type: GrantFiled: November 26, 2012Date of Patent: July 7, 2015Assignee: PS4 LUXCO S.A.R.L.Inventors: Fumiyuki Osanai, Toshio Sugano, Atsushi Hiraishi
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Publication number: 20150098289Abstract: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.Type: ApplicationFiled: October 7, 2014Publication date: April 9, 2015Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi
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Patent number: 8988952Abstract: Disclosed herein is a device that includes: a data strobe terminal; a data terminal; a first output driver coupled to the data strobe terminal; a second output driver coupled to the data terminal; and a data control circuit configured to enable the first and second output drivers to function as termination resistors in different timings from each other.Type: GrantFiled: December 26, 2012Date of Patent: March 24, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Atsushi Hiraishi, Toshio Sugano, Seiji Narui, Yasuhiro Takai
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Patent number: 8922029Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.Type: GrantFiled: February 1, 2012Date of Patent: December 30, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Atsushi Hiraishi, Toshio Sugano, Masahiro Yamaguchi, Yoji Nishio, Tsutomu Hara, Koichiro Aoki
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Patent number: 8680174Abstract: The present invention is directed to a water dispersion for ink-jet printing which realizes sufficient optical density and exhibits excellent filterability and storage stability; a water-based ink containing the water dispersion; and a process for producing the water dispersion or the water-based ink.Type: GrantFiled: December 11, 2009Date of Patent: March 25, 2014Assignee: Kao CorporationInventors: Atsushi Hiraishi, Kyoichi Shirota, Yuki Wakabayashi, Yasuhiro Doi
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Publication number: 20140001639Abstract: Disclosed herein is a device that includes a silicon interposer having wiring lines on first and second wiring layers. The wiring lines includes first, second and third wiring lines provided on the first wiring layer and a fourth wiring line provided on the second wiring layer. The third wiring line is arranged between the first and second wiring lines on the first wiring layer. The fourth wiring line is overlapped with the third wiring line. Each of the first, second and fourth wiring lines conveys a power supply potential to first and second semiconductor chips mounted on the silicon interposer, and the third wiring line conveys a first signal communicated between the first and second semiconductor chips.Type: ApplicationFiled: June 25, 2013Publication date: January 2, 2014Applicant: Elpida Memory, Inc.Inventors: Atsushi HIRAISHI, Toshio SUGANO, Yasuhiro TAKAI
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Patent number: 8422263Abstract: A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.Type: GrantFiled: June 3, 2010Date of Patent: April 16, 2013Assignee: Elpida Memory, Inc.Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi, Fumiyuki Osanai, Masayuki Nakamura, Hiroki Fujisawa
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Patent number: 8394871Abstract: The present invention provides [1] a water dispersion for ink-jet printing containing chain-like particles each containing anionic organic pigment particles and a cationic polymer, wherein the ratio of organic pigment primary particles forming the chain-like particles to all the pigment primary particles contained in the water dispersion is 10% by number or more; [2] a water-based ink for ink-jet printing containing the water dispersion; [3] a method for producing a water dispersion for ink-jet printing as described above in [1]; and [4] a water-based ink for ink-jet printing containing a water dispersion produced through the method. The water dispersion and water-based ink for ink-jet printing of the present invention realize excellent optical density.Type: GrantFiled: November 20, 2009Date of Patent: March 12, 2013Assignee: KAO CorporationInventors: Atsushi Hiraishi, Masayuki Narita, Takahiro Sato, Kyoichi Shirota, Yasuhiro Doi, Hiroyuki Yoshida, Yusuke Shimizu
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Patent number: 8198549Abstract: A multi-layer printed circuit board for mounting memories, includes: laminated wiring layers on which wiring is arranged; and a plurality of interlayer connection components which electrically connect at least two of the wiring layers. At least one of the plurality of interlayer connection components is a blind via-hole.Type: GrantFiled: December 20, 2007Date of Patent: June 12, 2012Assignee: Elpida Memory, Inc.Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi
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Publication number: 20120127675Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.Type: ApplicationFiled: February 1, 2012Publication date: May 24, 2012Applicant: ELPIDA MEMORY, INC.Inventors: ATSUSHI HIRAISHI, TOSHIO SUGANO, MASAHIRO YAMAGUCHI, YOJI NISHIO, TSUTOMU HARA, KOICHIRO AOKI
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Patent number: 8134239Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.Type: GrantFiled: September 29, 2008Date of Patent: March 13, 2012Assignee: Elpida Memory, Inc.Inventors: Atsushi Hiraishi, Toshio Sugano, Masahiro Yamaguchi, Yoji Nishio, Tsutomu Hara, Koichiro Aoki
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Publication number: 20110306708Abstract: The present invention is directed to a water dispersion for ink-jet printing which realizes sufficient optical density and exhibits excellent filterability and storage stability; a water-based ink containing the water dispersion; and a process for producing the water dispersion or the water-based ink.Type: ApplicationFiled: December 11, 2009Publication date: December 15, 2011Applicant: KAO CORPORATIONInventors: Atsushi Hiraishi, Kyoichi Shirota, Yuki Wakabayashi, Yasuhiro Doi
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Patent number: 8064236Abstract: In a multi-rank memory module having a terminal resistance of a data input/output pad 13 and a terminal resistance control pad 14 that inputs a signal that controls on/off of the terminal resistance, a high-speed operation is enabled with the aid of an enclosed terminal resistance, even in cases where the number of ranks is greater than that of terminal resistance control terminals (ODT terminals) provided on the memory module. To this end, a terminal resistance control pad 14 of a memory chip 12, having a longer length of an interconnect between a data bus 19 on a module substrate 8 and a data input/output pad 13, is connected to a terminal resistance control interconnect 18 or 21 to control the on/off of the terminal resistance from the ODT terminal. A terminal resistance control pad on a memory chip 11, having a shorter length of an interconnect between the data bus 19 on the module substrate and the data input/output pad 13, is connected to a fixed potential 20 to turn on the terminal resistance.Type: GrantFiled: June 3, 2009Date of Patent: November 22, 2011Assignee: Elpida Memory, Inc.Inventors: Yoji Nishio, Atsushi Hiraishi
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Publication number: 20110263752Abstract: The present invention provides [1] a water dispersion for ink-jet printing containing chain-like particles each containing anionic organic pigment particles and a cationic polymer, wherein the ratio of organic pigment primary particles forming the chain-like particles to all the pigment primary particles contained in the water dispersion is 10% by number or more; [2] a water-based ink for ink-jet printing containing the water dispersion; [3] a method for producing a water dispersion for ink-jet printing as described above in [1]; and [4] a water-based ink for ink-jet printing containing a water dispersion produced through the method. The water dispersion and water-based ink for ink-jet printing of the present invention realize excellent optical density.Type: ApplicationFiled: November 20, 2009Publication date: October 27, 2011Applicant: KAO CORPORATIONInventors: Atsushi Hiraishi, Masayuki Narita, Takahiro Sato, Kyoichi Shirota, Yasuhiro Doi, Hiroyuki Yoshida, Yusuke Shimizu
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Publication number: 20100309706Abstract: A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.Type: ApplicationFiled: June 3, 2010Publication date: December 9, 2010Applicant: Elpida Memory, Inc.Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi, Fumiyuki Osanai, Masayuki Nakamura, Hiroki Fujisawa
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Publication number: 20100312956Abstract: A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register buffers. Each of the data register buffers includes M input/output terminals (M is a positive integer equal to or larger than 1) that are connected to the data connectors via a first data line and N input/output terminals (N is a positive integer equal to or larger than 2M) that are connected to corresponding memory chips via second and third data lines, so that the number of the second and third data lines is N/M times the number of the first data lines. According to the present invention, because the load capacities of the second and third data lines are reduced by a considerable amount, it is possible to realize a considerably high data transfer rate.Type: ApplicationFiled: June 3, 2010Publication date: December 9, 2010Applicant: Elpida Memory, Inc.Inventors: Atsushi Hiraishi, Toshio Sugano, Fumiyuki Osanai, Masayuki Nakamura, Hiroki Fujisawa, Shunichi Saito