Abstract: A magnetic head includes a magnetic structure incorporating a write shield. The magnetic structure is formed to include a first magnetic layer, a second magnetic layer stacked on the first magnetic layer, and a seed layer. The first magnetic layer has a front end face located in the medium facing surface and a top surface. The second magnetic layer has a front end face located in the medium facing surface and a bottom surface. The top surface of the first magnetic layer includes a first region including an end located in the medium facing surface and a second region farther from the medium facing surface than the first region. The seed layer is not present on the first region of the top surface of the first magnetic layer but is present on the second region.

Abstract: A surface acoustic wave device according to the present invention includes a piezoelectric monocrystal substrate 10, and an interdigital electrode 20 configured of a base electrode layer 21 formed on the piezoelectric monocrystal substrate, the base electrode layer 21 being made of a conductive material, and an aluminum-containing main electrode layer 22 formed on the base electrode layer by epitaxial growth. The electrode 20 has an upper layer 23 formed on the main electrode layer 22, and the upper layer 23 is made of a conductive material that is different from materials for the main electrode layer and the base electrode layer and has a larger specific gravity than aluminum.

Abstract: A thin-film magnetic head includes a main magnetic pole layer, write shield layer, gap layer, and thin-film coils, which are laminated on a substrate. A return magnetic pole layer is spaced from the medium-opposing surface on the side opposite to the write shield layer with the main magnetic pole layer intervening therebetween. A connecting magnetic layer is formed using a magnetic material to connect the return magnetic pole layer to the write shield layer on the side closer to the medium-opposing surface than is the thin-film coil. The thin-film coil is wound as a flat spiral around the write shield layer. A part of the thin-film coil wound as the flat spiral is disposed only at a position distanced from the substrate than is the main magnetic pole layer.

Abstract: A magnetic head includes a shield, and first and second return path sections. The shield has an end face that is located in a medium facing surface to wrap around an end face of a main pole. The shield includes a bottom shield, two side shields, and a top shield. The first return path section is magnetically connected to the bottom shield and is greater than the bottom shield in length in a direction perpendicular to the medium facing surface. The second return path section magnetically couples the top shield and the main pole to each other. The coil includes a first portion that passes through a space defined by the main pole and the first return path section, and a second portion that passes through a space defined by the main pole and the second return path section.

Abstract: A memory device has a laminated chip package and a controller chip. In the laminated chip package, a plurality of memory chips are laminated. An interposed chip is laminated between the laminated chip package and the controller chip. The memory chips have a plurality of first wiring electrodes. The interposed chip has a plurality of second wiring electrodes. The second wiring electrodes are formed with a common arrangement pattern common with an arrangement pattern of a plurality of wiring electrodes for controller which are formed in the controller chip. The controller chip is laid on the interposed chip.

Abstract: A main package includes a plurality of stacked semiconductor chips and a plurality of first terminals associated with different ones of the semiconductor chips. An additional package includes an additional semiconductor chip and at least one second terminal electrically connected to the additional semiconductor chip. The additional semiconductor chip is to substitute for one of the plurality of semiconductor chips in the main package. The main package and the additional package are arranged in one of a plurality of relative positional relationships that is selected according to which one of the plurality of semiconductor chips in the main package is to be substituted with the additional semiconductor chip.

Abstract: In a manufacturing method for layered chip packages, a layered substructure with at least one additional package joined thereto is used to produce a plurality of layered chip packages. The layered substructure includes a plurality of main bodies to be separated from each other later. Each main body includes: a main part having top and bottom surfaces and including a plurality of layer portions stacked on each other; and a plurality of main terminals disposed on at least one of the top and bottom surfaces of the main part. The additional package includes an additional semiconductor chip and at least one additional terminal that is electrically connected to the additional semiconductor chip and in contact with at least one of the plurality of main terminals.

Abstract: A memory device has a laminated chip package and a controller chip. In the laminated chip package, a plurality of memory chips are laminated. An interposed chip is laminated between the laminated chip package and the controller chip. The memory chips have a plurality of first wiring electrodes. The interposed chip has a plurality of second wiring electrodes. The second wiring electrodes are formed with a common arrangement pattern common with an arrangement pattern of a plurality of wiring electrodes for controller which are formed in the controller chip. The controller chip is laid on the interposed chip.

Abstract: A layered chip package includes a main body and wiring. The main body has a main part. The main part has a top surface and a bottom surface and includes a plurality of layer portions that are stacked. The wiring includes a plurality of lines passing through all the plurality of layer portions. Each layer portion includes a semiconductor chip and a plurality of electrodes. The semiconductor chip has a first surface, and a second surface opposite thereto. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. The plurality of layer portions include two or more pairs of first and second layer portions in each of which the first and second layer portions are arranged so that the first or second surfaces of the respective semiconductor chips face each other. The plurality of electrodes include a plurality of first connection parts and a plurality of second connection parts.

Abstract: A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of stacked layer portions. A method of manufacturing the layered chip package includes the step of fabricating a layered substructure and the step of cutting the layered substructure. The layered substructure includes: a plurality of arrayed pre-separation main bodies; a plurality of accommodation parts disposed between two adjacent pre-separation main bodies; and a plurality of preliminary wires accommodated in the accommodation parts. The accommodation parts are formed in a photosensitive resin layer by photolithography. In the step of cutting the layered substructure, the plurality of pre-separation main bodies are separated from each other, and the wires are formed by the preliminary wires.

Abstract: A layered chip package includes a main body. The main body includes a main part, and further includes first terminals and second terminals disposed on the top and bottom surfaces of the main part, respectively. The main part includes first and second layer portions, and through electrodes penetrating them. The through electrodes are electrically connected to the first and second terminals. Each of the layer portions includes a semiconductor chip having a first surface and a second surface opposite thereto, and further includes surface electrodes. The surface electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the surface electrodes of the first layer portion. The second terminals are formed by using the surface electrodes of the second layer portion.

Abstract: A magnetic head includes a magnetic structure incorporating a write shield. The magnetic structure is formed to include a first magnetic layer, a second magnetic layer stacked on the first magnetic layer, and a seed layer. The first magnetic layer has a front end face located in the medium facing surface and a top surface. The second magnetic layer has a front end face located in the medium facing surface and a bottom surface. The top surface of the first magnetic layer includes a first region including an end located in the medium facing surface and a second region farther from the medium facing surface than the first region. The seed layer is not present on the first region of the top surface of the first magnetic layer but is present on the second region.

Abstract: A layered chip package includes a main body, and wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of semiconductor chips stacked, and a plurality of electrodes that electrically connect the semiconductor chips to the wires. A method of manufacturing the layered chip package includes the steps of: fabricating a substructure that includes an array of a plurality of pre-separation main bodies and a plurality of holes for accommodating a plurality of preliminary wires, the holes being formed between two adjacent pre-separation main bodies; forming the preliminary wires in the plurality of holes by plating; and cutting the substructure so that the plurality of pre-separation main bodies are separated from each other and the preliminary wires are split into two sets of wires of two separate main bodies, whereby a plurality of layered chip packages are formed.

Abstract: A thin-film magnetic head is constructed such that a main magnetic pole layer, a write shield layer, a gap layer, and a thin-film coil are laminated on a substrate. The thin-film magnetic head has a shield magnetic layer. The shield magnetic layer has a leading shield part. The leading shield part is disposed on a substrate side of the main magnetic pole layer. The leading shield part has a variable distance structure in which a rearmost part most distanced from the medium-opposing surface is distanced more from the main magnetic pole layer than is a foremost part on the main magnetic pole layer side.

Abstract: A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: a device region in contact with at least any one of the plurality of groove portions and having a semiconductor device formed therein; a surface insulating layer formed to cover the device region and constituting a surface layer of the semiconductor substrate; and a wiring electrode connected to the semiconductor device and formed in a protruding shape rising above a surface of the surface insulating layer. The semiconductor substrate can be manufactured by forming a plurality of groove portions along scribe lines; applying an insulating material to a surface on a side where the plurality of groove portions are formed to form a surface insulating layer; and forming a wiring electrode connected to the semiconductor device and in a protruding shape rising above a surface of the surface insulating layer, after the formation of the surface insulating layer.

Abstract: A thin film piezoelectric element of the present invention includes a substrate and a piezoelectric thin film stack formed on the substrate. The piezoelectric thin film stack includes a top electrode layer, a bottom electrode layer and a piezoelectric layer sandwiched between the top electrode layer and the bottom electrode layer, wherein the piezoelectric layer includes a first piezoelectric layer and a second piezoelectric layer whose compositions have different phase structures. The present invention can obtain high piezoelectric constants, enhanced coercive field strength, thereby enabling larger applied field strength without depolarization and achieving a large stroke for its applied device.

Abstract: A thin film piezoelectric element of the present invention includes a substrate and a piezoelectric thin film stack formed on the substrate. The piezoelectric thin film stack includes a top electrode layer, a bottom electrode layer and a piezoelectric layer sandwiched between the top electrode layer and the bottom electrode layer, wherein the piezoelectric layer includes a first piezoelectric layer and a second piezoelectric layer whose compositions have different phase structures. The present invention can obtain high piezoelectric constants, enhanced coercive field strength and good thermal stability, thereby enabling larger applied field strength without depolarization and achieving a large stroke for its applied device.

Abstract: In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions having a semiconductor device formed therein and insulated from each other, and a plurality of wiring electrodes connected to the semiconductor devices respectively formed in the plurality of device regions and extending from the device regions into the inside of the scribe-groove parts. The plurality of wiring electrodes are arranged in a partial arrangement pattern in which the wiring electrodes are arranged along only a part of four boundary sides, corresponding to boundaries between each of the device regions and the scribe-groove parts. Further, the plurality of wiring electrodes extend into the scribe-groove part from only one of two device regions adjacent to each other with the scribe-groove part therebetween.

Abstract: A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. Each layer portion includes a semiconductor chip having a first surface and a second surface opposite thereto, and includes a plurality of electrodes. The electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the electrodes of the first layer portion, and the second terminals are formed by using the electrodes of the second layer portion.

Abstract: A main package includes a plurality of stacked semiconductor chips and a plurality of first terminals associated with different ones of the semiconductor chips. An additional package includes an additional semiconductor chip and at least one second terminal electrically connected to the additional semiconductor chip. The additional semiconductor chip is to substitute for one of the plurality of semiconductor chips in the main package. The main package and the additional package are arranged in one of a plurality of relative positional relationships that is selected according to which one of the plurality of semiconductor chips in the main package is to be substituted with the additional semiconductor chip.