Patents by Inventor Atsushi Iijima

Atsushi Iijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8426946
    Abstract: In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein, a first wiring electrode and a second wiring electrode extend to the inside of a interposed groove part from a first device region and a second device region respectively, and are separated from each other. In the laminated semiconductor substrate, a through hole which the first wiring electrode appears is formed. The laminated semiconductor substrate has a through electrode. The through electrode is contact with all of the first wiring electrodes appearing in the through hole. The laminated semiconductor substrate has a plurality of laminated chip regions.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: April 23, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
  • Patent number: 8426948
    Abstract: In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have electromagnetic shielding layer formed in regions other than the scribe-groove parts using a ferromagnetic body. Further, in the laminated semiconductor substrate, a through hole which penetrates the plurality of semiconductor substrates laminated in a laminated direction is formed in the scribe-groove part, and the laminated semiconductor substrate has a through electrode penetrating the plurality of semiconductor substrates through the through hole.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: April 23, 2013
    Assignees: Headway Technologies, Inc., Sae Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
  • Patent number: 8426981
    Abstract: A composite layered chip package includes first and second subpackages that are stacked. Each subpackage includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface; first terminals disposed on the top surface of the main part; and second terminals disposed on the bottom surface of the main part. The first and second terminals are electrically connected to the wiring. The first and second subpackages are arranged in a specific relative positional relationship, different from a reference relative positional relationship, with each other.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: April 23, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
  • Patent number: 8426947
    Abstract: In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have an electromagnetic shielding layer formed using a ferromagnetic body. The electromagnetic shielding layer is formed in a shielding region except the extending zone. The extending zone is set a part which the wiring electrode crosses, in a peripheral edge part of the device region.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: April 23, 2013
    Assignees: Headway Technologies, Inc., SAE Magentics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
  • Patent number: 8421243
    Abstract: A layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions stacked; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. The plurality of layer portions include a first-type layer portion and a second-type layer portion. The first-type layer portion includes a conforming semiconductor chip, and a plurality of first-type electrodes that are connected to the semiconductor chip and the wiring. The second-type layer portion includes a defective semiconductor chip, and a plurality of second-type electrodes that are connected to the wiring and not to the semiconductor chip.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: April 16, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Hiroshi Ikejima, Atsushi Iijima
  • Patent number: 8416528
    Abstract: A magnetic head includes a main pole and a return path section located above a top surface of a substrate. The main pole has an end face located in a medium facing surface. The return path section is located on the front side in the direction of travel of a recording medium relative to the main pole and is farther from the top surface of the substrate than is the main pole. The return path section has: a front end face located on the front side of the main pole in the medium facing surface; and an inclined surface located on the front side and connected to the front end face. The inclined surface is not exposed in the medium facing surface. An angle greater than 90° is formed between the front end face and the inclined surface.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: April 9, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Shigeki Tanemura, Kazuki Sato, Yukinori Ikegawa, Atsushi Iijima, Tatsuya Shimizu
  • Publication number: 20130075935
    Abstract: A composite layered chip package includes first and second subpackages that are stacked. Each subpackage includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface; first terminals disposed on the top surface of the main part; and second terminals disposed on the bottom surface of the main part. The first and second terminals are electrically connected to the wiring. The first and second subpackages are arranged in a specific relative positional relationship, different from a reference relative positional relationship, with each other.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 28, 2013
    Applicants: SAE MAGNETICS (H.K.) LTD., HEADWAY TECHNOLOGIES, INC.
    Inventors: Yoshitaka SASAKI, Hiroyuki ITO, Atsushi IIJIMA
  • Patent number: 8395972
    Abstract: A thermally assisted magnetic head is formed by performing a head forming process, a mounting part forming process and a light source mounting process in that order. In the head forming process, a planned area is secured on a light source placing surface of a slider substrate, then a magnetic head part is formed on a head area other than the planned area and a spacer for securing a mounting space for the laser diode is formed on the planned area. In the mounting part forming process, a light source mounting part is formed by removing the spacer. In the light source mounting process, a laser diode is mounted on the light source mounting part formed by the mounting part forming step.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: March 12, 2013
    Assignees: Headway Technologies, Inc., TDK Corporation
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
  • Publication number: 20130057987
    Abstract: A thin-film magnetic head is constructed such that a main magnetic pole layer, a write shield layer, a gap layer, and a thin-film coil are laminated on a substrate. The thin-film magnetic head has a leading shield part opposing the main magnetic pole layer on the substrate side of the main magnetic pole layer. The thin-film magnetic head has a substrate side coil layer disposed between the main magnetic pole layer and the substrate. In the thin-film magnetic head, a space between a lower end face of the leading shield part and the substrate and a space between an upper end face in the substrate side coil layer and the substrate are formed equal to each other.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 7, 2013
    Applicants: SAE MAGNETICS (H.K.) LTD., HEADWAY TECHNOLOGIES, INC.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Shigeki Tanemura, Kazuki Sato, Atsushi Iijima
  • Patent number: 8390955
    Abstract: A thin-film magnetic head is constructed such that a main magnetic pole layer, a write shield layer, a gap layer, and a thin-film coil are laminated on a substrate. The thin-film magnetic head has a leading shield part opposing the main magnetic pole layer on the substrate side of the main magnetic pole layer. The thin-film magnetic head has a substrate side coil layer disposed between the main magnetic pole layer and the substrate. In the thin-film magnetic head, a space between a lower end face of the leading shield part and the substrate and a space between an upper end face in the substrate side coil layer and the substrate are formed equal to each other.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: March 5, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Shigeki Tanemura, Kazuki Sato, Atsushi Iijima
  • Publication number: 20130038966
    Abstract: A magnetic head includes: a main pole; a coil; a first shield having an end face that is located in a medium facing surface at a position forward of an end face of the main pole along a direction of travel of a recording medium; and a first return path section disposed forward of the main pole along the direction of travel of the recording medium. The first return path section connects part of the main pole away from the medium facing surface to the first shield so that a first space is defined. The coil includes a first portion having a planar spiral shape and wound around a core part of the first return path section. The first portion includes first and second coil elements that each extend through the first space. No part of the coil other than the first and second coil elements exists in the first space.
    Type: Application
    Filed: August 12, 2011
    Publication date: February 14, 2013
    Applicants: SAE MAGNETICS (H.K.) LTD., HEADWAY TECHNOLOGIES, INC.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Kazuki Sato, Atsushi Iijima
  • Patent number: 8362602
    Abstract: A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. Each layer portion includes a semiconductor chip. The plurality of second terminals are positioned to overlap the plurality of first terminals as viewed in a direction perpendicular to the top surface of the main body. A plurality of pairs of first and second terminals that are electrically connected via the wires include a plurality of pairs of a first terminal and a second terminal that are positioned not to overlap each other.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: January 29, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Hiroshi Ikejima, Atsushi Iijima
  • Publication number: 20130020723
    Abstract: A composite layered chip package includes a plurality of subpackages stacked on each other. Each subpackage includes a main body and wiring. The main body includes a main part including a plurality of layer portions, and further includes first terminals and second terminals that are disposed on top and bottom surfaces of the main part, respectively. The wiring is electrically connected to the first and second terminals. The number of the plurality of layer portions included in the main part is the same for all the plurality of subpackages, and the plurality of layer portions in every subpackage include at least one first-type layer portion. In each of at least two of the subpackages, the plurality of layer portions further include at least one second-type layer portion. The first-type layer portion includes a semiconductor chip connected to the wiring, whereas the second-type layer portion includes a semiconductor chip not connected to the wiring.
    Type: Application
    Filed: July 18, 2011
    Publication date: January 24, 2013
    Applicants: SAE MAGNETICS (H.K.) LTD., HEADWAY TECHNOLOGIES, INC.
    Inventors: Yoshitaka SASAKI, Hiroyuki ITO, Hiroshi IKEJIMA, Atsushi IIJIMA
  • Patent number: 8358015
    Abstract: A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: January 22, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Hiroshi Ikejima, Atsushi Iijima
  • Patent number: 8358487
    Abstract: A thin-film magnetic head is constructed such that a main magnetic pole layer, a write shield layer, a gap layer, and a thin-film coil are laminated on a substrate. The thin-film coil has a coil-layer. The coil-layer has a turn part arranged closer to an ABS than is a rear end part of the main magnetic pole layer farthest from the ABS. Regarding a substrate side coil-layer, arranged between the main magnetic pole layer and the substrate, of the coil-layer, a thickness of a non-corresponding magnetic pole part other than a magnetic pole corresponding part corresponding to an arrangement space of the main magnetic pole layer is larger than a thickness of the magnetic pole corresponding part.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: January 22, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Kazuki Sato, Atsushi Iijima
  • Patent number: 8345384
    Abstract: A main pole has a top surface and a bottom end that each include first, second, and third portions arranged contiguously in this order of increasing distance from a medium facing surface. A first virtual plane and a second virtual plane are assumed. The first virtual plane passes through an end of an end face of the main pole located forward in the direction of travel of a recording medium and is perpendicular to the medium facing surface and to the direction of travel of the recording medium. The second virtual plane passes through an end of the end face of the main pole located backward in the direction of travel of the recording medium and is perpendicular to the medium facing surface and to the direction of travel of the recording medium. The first and third portions are inclined relative to the first and second virtual planes and the medium facing surface. The second portion is parallel to the first and second virtual planes.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: January 1, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Kazuki Sato, Shigeki Tanemura, Hironori Araki, Atsushi Iijima
  • Patent number: 8345382
    Abstract: A magnetic head includes a coil, a main pole, a gap part, a write shield, and a return path section. The return path section includes a yoke part with a first coupling layer connected to the write shield and a second coupling layer magnetically coupling the first coupling layer to the yoke part. The second coupling layer has an end face facing toward a medium facing surface and located away from the medium facing surface. The coil includes i) a first coil element disposed with the first coupling layer interposed between the medium facing surface and the first coil element and ii) a plurality of second coil elements aligned perpendicularly to the medium facing surface and disposed with the second coupling layer interposed between the medium facing surface and the second coil elements. The first coil element being interposed between the main pole and the second coil elements.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: January 1, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Kazuki Sato, Atsushi Iijima
  • Patent number: 8344494
    Abstract: A layered chip package includes a main body and wiring. The main body includes a main part including a plurality of stacked layer portions, and a plurality of terminals disposed on the top and bottom surfaces of the main part. The wiring includes a plurality of lines electrically connected to the plurality of terminals. The plurality of lines include a plurality of common lines and a plurality of layer-dependent lines. Each of the plurality of layer portions includes: a plurality of common electrodes electrically connected to the plurality of common lines; a plurality of non-contact electrodes that are electrically connected to the layer-dependent lines and are not in contact with the semiconductor chip in the layer portion; and a selective connection electrode selectively electrically connected to only the layer-dependent line that the layer portion uses among the plurality of layer-dependent lines. The layer-dependent lines are greater than the common lines in maximum width.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: January 1, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Hiroshi Ikejima, Atsushi Iijima
  • Publication number: 20120313260
    Abstract: A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion.
    Type: Application
    Filed: June 9, 2011
    Publication date: December 13, 2012
    Applicants: HEADWAY TECHNOLOGIES, INC.
    Inventors: Yoshitaka SASAKI, Hiroyuki ITO, Hiroshi IKEJIMA, Atsushi IIJIMA
  • Publication number: 20120314323
    Abstract: A magnetic head includes a coil, a main pole, a gap part, a write shield, and a return path section. The return path section includes a yoke part and first and second coupling layers. The first coupling layer is connected to the write shield. The second coupling layer magnetically couples the first coupling layer to the yoke part, and has an end face facing toward a medium facing surface and located away from the medium facing surface. The coil includes a first coil element and a plurality of second coil elements that each extend to pass through a space defined by the main pole, the gap part, the write shield, and the return path section. The first coil element is disposed with the first coupling layer interposed between the medium facing surface and the first coil element. The second coil elements are disposed with the second coupling layer interposed between the medium facing surface and the second coil elements, and with the first coil element interposed between the main pole and the second coil elements.
    Type: Application
    Filed: June 9, 2011
    Publication date: December 13, 2012
    Applicants: SAE MAGNETICS (H.K.) LTD., HEADWAY TECHNOLOGIES, INC.
    Inventors: Yoshitaka SASAKI, Hiroyuki ITO, Kazuki SATO, Atsushi IIJIMA