Abstract: A halt period is inserted between a drive period in an odd-numbered field and a drive period in an even-numbered field in interlace driving. When drive signals driving subpixels are time-divisionally supplied to the display panel in units of subpixel types, switch control signals controlling source line switches which distribute the drive signals associated with respective subpixels to the corresponding source lines are generated so that the number of switching of the source line switches are reduced.

Abstract: A semiconductor device configured to drive a display panel in a display period, and perform touch sensing on the display panel in a touch sensing period after the display period. In a last horizontal sync period of the display period, the semiconductor device drives a first source line with a drive voltage of a first polarity, and a second source line with a drive voltage of a second polarity different from the first polarity. is the semiconductor is configured to output a first dummy pulse having first polarity and a voltage level based on the second display data to the first source line in a transition period between the display period and the touch sensing period.

Abstract: A semiconductor device has a first mode in which the semiconductor device is used alone and a second mode in which the semiconductor device is used in combination with another semiconductor device. In case that one driven device is driven using the semiconductor device in the first mode and the second mode, power supply lines are caused to allow electrical conduction to each other outside of each semiconductor device in order to cancel errors of operation power supply voltages of each semiconductor device. In case that a power supply unit of each semiconductor device is operable by receiving an instruction for release of a low power consumption state, a supply start timing of the operation power supply voltages in the second mode is delayed as compared to that in the first mode.

Abstract: A semiconductor device has a first mode in which the semiconductor device is used alone and a second mode in which the semiconductor device is used in combination with another semiconductor device. Incase that one driven device is driven using the semiconductor device in the first mode and the second mode, power supply lines are caused to allow electrical conduction to each other outside of each semiconductor device in order to cancel errors of operation power supply voltages of each semiconductor device. In case that a power supply unit of each semiconductor device is operable by receiving an instruction for release of a low power consumption state, a supply start timing of the operation power supply voltages in the second mode is delayed as compared to that in the first mode.

Abstract: A halt period is inserted between a drive period in an odd-numbered field and a drive period in an even-numbered field in interlace driving. When drive signals driving subpixels are time-divisionally supplied to the display panel in units of subpixel types, switch control signals controlling source line switches which distribute the drive signals associated with respective subpixels to the corresponding source lines are generated so that the number of switching of the source line switches are reduced.

Abstract: In case that a terminal gradation signal output terminal in a pre-stage display driver and an initial gradation signal output terminal in a next-stage display driver of a plurality of display drivers which are arranged in parallel are used in driving the same gradation signal electrode of a display panel, an output of dummy data from the other gradation signal output terminal which mutually competes with an output timing of a gradation signal from one gradation signal output terminal between both the gradation signal output terminals is suppressed by high impedance control of a corresponding gradation signal output terminal.

Abstract: A semiconductor device has a first mode in which the semiconductor device is used alone and a second mode in which the semiconductor device is used in combination with another semiconductor device. Incase that one driven device is driven using the semiconductor device in the first mode and the second mode, power supply lines are caused to allow electrical conduction to each other outside of each semiconductor device in order to cancel errors of operation power supply voltages of each semiconductor device. In case that a power supply unit of each semiconductor device is operable by receiving an instruction for release of a low power consumption state, a supply start timing of the operation power supply voltages in the second mode is delayed as compared to that in the first mode.

Abstract: A circuit apparatus is provided for driving source electrodes of a display panel based on image data and to control a backlight of the display panel. For example, the circuit apparatus includes a display drive (DD) circuit having a parameter generation (PG) part and an image data conversion (IDC) part. The PG part is operable to generate an image data-conversion parameter and a backlight control parameter based on a brightness distribution of the image data of one frame. The IDC part is operable to convert the image data based on the image data-conversion parameter. The DD circuit is operable to output source signals generated based on the converted image data and output, control the backlight based on the backlight control parameter, and stop an action of the parameter generation part in response to no change in the image data of one frame from image data of a preceding frame being detected.

Abstract: In case that a terminal gradation signal output terminal in a pre-stage display driver and an initial gradation signal output terminal in a next-stage display driver of a plurality of display drivers which are arranged in parallel are used in driving the same gradation signal electrode of a display panel, an output of dummy data from the other gradation signal output terminal which mutually competes with an output timing of a gradation signal from one gradation signal output terminal between both the gradation signal output terminals is suppressed by high impedance control of a corresponding gradation signal output terminal.

Abstract: A controller 3 of a memory card is a provided with a command decoding circuit 6 for decoding commands issued by a host HT, a command enable register 8 in which the validity or invalidity of the received command, and a command detection signal generating circuit 7 for detecting a valid command on the basis of the result of decoding by the command decoding circuit 6 and a value set by the command enable register 8. If the command enable register 8 receives a validly set command, the command detection signal generating circuit 7 will supply a detection signal to a control unit 4 to execute processing prescribed for each command. the command enable register 8 receives an invalidly set command, no detection signal will be supplied, and the command will be ignored.

Abstract: The present invention provides a nonvolatile memory card in which a program is added, modified, changed, or the like by selecting arbitrary firmware on a flash memory from a plurality of pieces of firmware on flash memories. In a memory card, in addition to a program stored in a built-in ROM, firmware on flash memories as programs for adding, changing, modifying, or the like of a function such as a patch program are stored. Firmware on a flash memory which is desired to be made valid is set in a parameter sector or the like and is loaded into an external RAM, and the CPU of a control logic executes a process.

Abstract: A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.

Abstract: When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.

Abstract: Whether an initial command outputted from a host is ‘CMD1’ or ‘CMD55+CMD41’ is detected with an initial command detection portion 8, and the result of detection is set in an SD/MMC register 13. Reset process for hardware and that for firmware are carried out based on the result of detection set in the SD/MMC register 13. Thereafter, a microcomputer 7 sets data indicating in which mode, MultiMedia Card mode or SD mode, the firmware reset process was carried out, in a F/W process SD/MMC register 14. A H/W-F/W mode comparison circuit 15 compares data in the SD/MMC register 13 with data in the F/W process SD/MMC register 14. If these data agree with each other, busy state is released, and command wait state is established. If they disagree with each other, a disagreement occurrence detection signal is outputted to the microcomputer 7, and power-on reset processing is performed again.

Abstract: A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition.

Abstract: The present invention provides a nonvolatile memory card in which a program is added, modified, changed, or the like by selecting arbitrary firmware on a flash memory from a plurality of pieces of firmware on flash memories. In a memory card, in addition to a program stored in a built-in ROM, firmware on flash memories as programs for adding, changing, modifying, or the like of a function such as a patch program are stored. Firmware on a flash memory which is desired to be made valid is set in a parameter sector or the like and is loaded into an external RAM, and the CPU of a control logic executes a process.

Abstract: A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.

Abstract: The present invention is directed to suppress data loss caused by power shut-down during a rewriting process and to shorten time required to make a depletion check. A nonvolatile memory apparatus includes a rewritable nonvolatile memory and a card controller. The nonvolatile memory has a physical address area corresponding to a logical address and a save area. In response to a data rewrite instruction on a required logical address, the card controller stores data in a predetermined physical address area corresponding to the logical address to the save area and rewrites the data stored in the physical address area. When rewriting of the physical address area is incomplete, the card controller rewrites the data in the physical address area with the data stored in the save area. Thus, data loss caused by the power shut-down can be suppressed by data backup, and it is sufficient to make the depletion check in two places of the save area and the physical address area.

Abstract: A card device has a regulator (5), a first internal circuit (6) and a second internal circuit (7), and the regulator supplies, to the second internal circuit, an internal voltage generated by dropping an external voltage (VCC) when the external voltage is high, and exactly supplies the external voltage as the internal voltage to the second internal circuit when the external voltage is low, and the external voltage is supplied as an operating power source to the first internal circuit and a transition to a low consumed power state is carried out if a command is not input for a certain period. The card device stops the operation of the regulator and suppresses the supply of the internal voltage to the second internal circuit in the transition to the low consumed power state. In the low consumed power state, consequently, it is possible to suppress a power consumption in each of the regulator and the second internal circuit in the card device.

Abstract: The present invention provides a nonvolatile memory card in which a program is added, modified, changed, or the like by selecting arbitrary firmware on a flash memory from a plurality of pieces of firmware on flash memories. In a memory card, in addition to a program stored in a built-in ROM, firmware on flash memories as programs for adding, changing, modifying, or the like of a function such as a patch program are stored. Firmware on a flash memory which is desired to be made valid is set in a parameter sector or the like and is loaded into an external RAM, and the CPU of a control logic executes a process.