Abstract: Novel and useful system and methods of functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The NN processor incorporates functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well. The safety mechanisms cover data stream fault detection, software defined redundant allocation, cluster interlayer safety, cluster intralayer safety, layer control unit (LCU) instruction addressing, weights storage safety, and neural network intermediate results storage safety.

Abstract: A controller is arranged to: receive a first decoded beacon frame which includes a first indication of a first data transmission; receive a second decoded beacon frame which includes a second indication of a second data transmission; compare the first and second decoded beacon frames to determine common bytes in the first and second decoded beacon frames; determine an expected time of receiving the common bytes in a third beacon frame; control a device to enter into a low power mode; and control the device to wake up from the low power mode at a time to receive and decode at least a portion of the third beacon frame, in which the time to wake up is based on the expected time to receive the common bytes instead of based on an expected time to receive a preamble at a start of the third beacon frame.

Abstract: Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The mechanisms address ANN system level safety in situ, as a system level strategy tightly coupled with the processor architecture. The NN processor incorporates several functional safety concepts that function to detect and promptly flag and report an error with some mechanisms capable of correction as well.

Abstract: A circuit includes a controller configured to: receive a first decoded beacon frame which includes a first indication of a first data transmission; receive a second decoded beacon frame which includes a second indication of a second data transmission; compare the first and second decoded beacon frames to determine common bytes in the first and second decoded beacon frames; determine an expected time of receiving the common bytes in a third beacon frame; control a device to enter into a low power mode; and control the device to wake up from the low power mode at a time to receive and decode at least a portion of the third beacon frame, in which the time to wake up is based on the expected time to receive the common bytes instead of based on an expected time to receive a preamble at a start of the third beacon frame.

Abstract: A novel and useful neural network (NN) processing core incorporating inter-device connectivity and adapted to implement artificial neural networks (ANNs). A chip-to-chip interface spreads a given ANN model across multiple devices in a seamless manner. The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level.

Abstract: A Wi-Fi device includes a controller coupled to a writeable memory implementing a MAC and PHY layer and to a transceiver. Connection data stored in the writeable memory includes Wi-Fi connection parameters including ?1 router MAC level information or a most recently utilized (MRU) channel used, and IP addresses including ?1 of an IP address of the Wi-Fi device, IP address of the MRU router, an IP address of a MRU target server, and an IP address of a network connected device. An accelerated reconnecting to a Wi-Fi network algorithm is implemented by the processor is for starting from being in a network disconnected state, establishing current connection parameters for a current Wi-Fi network connection using the Wi-Fi connection parameters for at least one MAC layer parameter for the MAC layer.

Abstract: A novel and useful system and method of improved power performance and lowered memory requirements for an artificial neural network based on packing memory utilizing several structured sparsity mechanisms. The invention applies to neural network (NN) processing engines adapted to implement mechanisms to search for structured sparsity in weights and activations, resulting in a considerably reduced memory usage. The sparsity guided training mechanism synthesizes and generates structured sparsity weights. A compiler mechanism within a software development kit (SDK), manipulates structured weight domain sparsity to generate a sparse set of static weights for the NN. The structured sparsity static weights are loaded into the NN after compilation and utilized by both the structured weight domain sparsity mechanism and the structured activation domain sparsity mechanism.

Abstract: A novel and useful system and method of improved power performance and lowered memory requirements for an artificial neural network based on packing memory utilizing several structured sparsity mechanisms. The invention applies to neural network (NN) processing engines adapted to implement mechanisms to search for structured sparsity in weights and activations, resulting in a considerably reduced memory usage. The sparsity guided training mechanism synthesizes and generates structured sparsity weights. A compiler mechanism within a software development kit (SDK), manipulates structured weight domain sparsity to generate a sparse set of static weights for the NN. The structured sparsity static weights are loaded into the NN after compilation and utilized by both the structured weight domain sparsity mechanism and the structured activation domain sparsity mechanism.

Abstract: A circuit includes a controller configured to: receive a first decoded beacon frame which includes a first indication of a first data transmission; receive a second decoded beacon frame which includes a second indication of a second data transmission; compare the first and second decoded beacon frames to determine common bytes in the first and second decoded beacon frames; determine an expected time of receiving the common bytes in a third beacon frame; control a device to enter into a low power mode; and control the device to wake up from the low power mode at a time to receive and decode at least a portion of the third beacon frame, in which the time to wake up is based on the expected time to receive the common bytes instead of based on an expected time to receive a preamble at a start of the third beacon frame.

Abstract: A novel and useful system and method of improved power performance and lowered memory requirements for an artificial neural network based on packing memory utilizing several structured sparsity mechanisms. The invention applies to neural network (NN) processing engines adapted to implement mechanisms to search for structured sparsity in weights and activations, resulting in a considerably reduced memory usage. The sparsity guided training mechanism synthesizes and generates structured sparsity weights. A compiler mechanism within a software development kit (SDK), manipulates structured weight domain sparsity to generate a sparse set of static weights for the NN. The structured sparsity static weights are loaded into the NN after compilation and utilized by both the structured weight domain sparsity mechanism and the structured activation domain sparsity mechanism.

Abstract: A Wi-Fi device includes a controller coupled to a writeable memory implementing a MAC and PHY layer and to a transceiver. Connection data stored in the writeable memory includes Wi-Fi connection parameters including?1 router MAC level information or a most recently utilized (MRU) channel used, and IP addresses including?1 of an IP address of the Wi-Fi device, IP address of the MRU router, an IP address of a MRU target server, and an IP address of a network connected device. An accelerated reconnecting to a Wi-Fi network algorithm is implemented by the processor is for starting from being in a network disconnected state, establishing current connection parameters for a current Wi-Fi network connection using the Wi-Fi connection parameters for at least one MAC layer parameter for the MAC layer.

Abstract: A novel and useful neural network (NN) processing core adapted to implement artificial neural networks (ANNs) and incorporating processing circuits having compute and local memory elements. The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level.

Abstract: A novel and useful system and method of accessing multi-dimensional data in memory. The invention is applicable to neural network (NN) processing engines adapted to implement artificial neural networks (ANNs). The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level.

Abstract: A novel and useful system and method of data driven quantization optimization of weights and input data in an artificial neural network (ANN). The system reduces quantization implications (i.e. error) in a limited resource system by employing the information available in the data actually observed by the system. Data counters in the layers of the network observe the data input thereto. The distribution of the data is used to determine an optimum quantization scheme to apply to the weights, input data, or both. The mechanism is sensitive to the data observed at the input layer of the network. As a result, the network auto-tunes to optimize the instance specific representation of the network. The network becomes customized (i.e. specialized) to the inputs it observes and better fits itself to the subset of the sample space that is applicable to its actual data flow. As a result, nominal process noise is reduced and detection accuracy improves.

Abstract: In a described example, an integrated circuit includes an input coupled to receive a plurality of beacon frames, the beacon frames include an indication of data transmissions available for a device that includes the integrated circuit. The integrated circuit also includes a controller configured to compare the plurality of beacon frames to determine a plurality of bytes prior to the indication of data transmission available that is present in each of the plurality of beacon frames and is configured to provide a signal indicating a low power mode in which the device does not receive transmissions and to provide a signal indicating a wake mode at a selected time before transmission of the plurality of bytes in a subsequent beacon transmission.

Abstract: A novel and useful neural network (NN) processing core adapted to implement artificial neural networks (ANNs) and incorporating configurable and programmable sliding window based memory access. The memory mapping and allocation scheme trades off random and full access in favor of high parallelism and static mapping to a subset of the overall address space. The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio.

Abstract: Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The various mechanisms of the present invention address ANN system level safety in situ, as a system level strategy that is tightly coupled with the processor architecture. The NN processor incorporates several functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well.

Abstract: Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The various mechanisms of the present invention address ANN system level safety in situ, as a system level strategy that is tightly coupled with the processor architecture. The NN processor incorporates several functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well.

Abstract: Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The various mechanisms of the present invention address ANN system level safety in situ, as a system level strategy that is tightly coupled with the processor architecture. The NN processor incorporates several functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well.

Abstract: Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The various mechanisms of the present invention address ANN system level safety in situ, as a system level strategy that is tightly coupled with the processor architecture. The NN processor incorporates several functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well.