Abstract: A novel and useful neural network (NN) processing core adapted to implement artificial neural networks (ANNs) and incorporating configurable and programmable sliding window based memory access. The memory mapping and allocation scheme trades off random and full access in favor of high parallelism and static mapping to a subset of the overall address space. The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio.

Abstract: A novel and useful neural network (NN) processing core adapted to implement artificial neural networks (ANNs) and incorporating processing circuits having compute and local memory elements. The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level.

Abstract: A novel and useful system and method of data driven quantization optimization of weights and input data in an artificial neural network (ANN). The system reduces quantization implications (i.e. error) in a limited resource system by employing the information available in the data actually observed by the system. Data counters in the layers of the network observe the data input thereto. The distribution of the data is used to determine an optimum quantization scheme to apply to the weights, input data, or both. The mechanism is sensitive to the data observed at the input layer of the network. As a result, the network auto-tunes to optimize the instance specific representation of the network. The network becomes customized (i.e. specialized) to the inputs it observes and better fits itself to the subset of the sample space that is applicable to its actual data flow. As a result, nominal process noise is reduced and detection accuracy improves.

Abstract: A novel and useful neural network (NN) processing core incorporating inter-device connectivity and adapted to implement artificial neural networks (ANNs). A chip-to-chip interface spreads a given ANN model across multiple devices in a seamless manner. The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level.

Abstract: A novel and useful augmented artificial neural network (ANN) incorporating an existing artificial neural network (ANN) coupled to a supplemental ANN and a FIFO for storing historical output values of the network. The augmented ANN exploits the redundant nature of information present in an input data stream. The addition of the supplemental ANN along with a FIFO enables the augmented network to look back into the past in making a decision for the current frame. It provides context aware object presence as well as lowers the rate of false detections and misdetections. The output of the existing ANN is stored in a FIFO to create a lookahead system in which both past output values of the supplemental ANN and ‘future’ values of the output of the existing ANN are used in making a decision for the current frame. In addition, the mechanism does not require retraining the entire neural network nor does it require data set labeling.

Abstract: A novel and useful system and method of accessing multi-dimensional data in memory. The invention is applicable to neural network (NN) processing engines adapted to implement artificial neural networks (ANNs). The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level.

Abstract: A novel and useful neural network (NN) processing core adapted to implement artificial neural networks (ANNs) and incorporating strictly separate control and data planes. The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level. Dynamic resource assignment agility is provided which can be adjusted as required depending on resource availability and capacity of the device.

Abstract: In a described example, an integrated circuit includes an input coupled to receive a plurality of beacon frames, the beacon frames include an indication of data transmissions available for a device that includes the integrated circuit. The integrated circuit also includes a controller configured to compare the plurality of beacon frames to determine a plurality of bytes prior to the indication of data transmission available that is present in each of the plurality of beacon frames and is configured to provide a signal indicating a low power mode in which the device does not receive transmissions and to provide a signal indicating a wake mode at a selected time before transmission of the plurality of bytes in a subsequent beacon transmission.

Abstract: Systems and methods for enabling proximity operations with long-range wireless communication interfaces are described. In an illustrative, non-limiting embodiment, a method may include transmitting a plurality of data packets using a WiFi interface of a first device, where each data packet has a signal strength following a predetermined pattern; and receiving an indication, via the WiFi interface, of whether the predetermined pattern has been identified by a second device.

Abstract: A novel and useful apparatus for and method of a unified IO controller well suited for use in integrated wireless devices incorporating multiple functions. The unified IO controller is operative to provide a single host interface PHY/MAC that is shared among all functions on the controller. The invention provides an IO protocol handler comprising common and unified logic that provides IO access to any function on the device. The common and unified IO PHY interface logic is shared between multiple functions within the same device (e.g., WLAN, GPS, Bluetooth, etc.). This implementation provides optimized hardware partitioning in which common SDIO logic serves multiple functions thereby eliminating the need to provide a protocol handler for each function, reducing pin count, power consumption and die size, since the SDIO protocol handling is implemented in a shared module.

Abstract: A system and method is disclosed that enables a peripheral or slave device to seamlessly transition in and out of sleep state while remaining completely transparent to host software. When the device is in a sleep mode and incoming data is detected, the device begins a wake-up procedure and data is routed to a first, transitional memory. The size of the transitional memory is selected such that it is capable of buffering data received during time required for the system memory to stabilize from wake-up. Once a second, extended memory is stabilized, the data is buffered from the transitional memory to the extended memory. The device resumes normal operation when its processor has initialized and can read data from the extended memory.

Abstract: As one example, a method includes sending a request in a secure wireless network from a first device. The request includes a predetermined information element indicating the first device is capable of implementing a peer configuration method. In response to receiving a reply that includes the predetermined information element from at least one other device, which is already operating in the wireless network, the method also includes establishing a secure channel between the first device and the other device. The method also includes receiving at the first device network configuration data via the secure channel, the network configuration data sufficient to enable the first device to connect to the wireless network.

Abstract: A wireless universal serial bus (USB) system that includes a wireless USB host, a first wireless USB device, and a second wireless USB device. The wireless USB host is configured to wirelessly transmit a beacon over a wireless USB network based on a wireless USB protocol. The first and second wireless USB devices are configured to exchange wireless packets with the wireless USB host. The beacon designates the wireless USB network address access times for the first and second wireless USB devices.

Abstract: A dual platform communication controller, a method of controlling communication of data packets based on different communication standards and a wireless transceiver. In one embodiment, the dual platform communication controller includes: (1) a signal interpreter configured to recognize first data packets based on a first communication standard and second data packets based on a second communication standard and (2) a traffic manager coupled to the signal interpreter and configured to dynamically control communication of the second data packets including active second data packets and allocate bandwidth for communication of the first and second data packets.

Abstract: Systems and methods for enabling proximity operations with long-range wireless communication interfaces are described. In an illustrative, non-limiting embodiment, a method may include transmitting a plurality of data packets using a WiFi interface of a first device, where each data packet has a signal strength following a predetermined pattern; and receiving an indication, via the WiFi interface, of whether the predetermined pattern has been identified by a second device.

Abstract: A system and method is disclosed that enables a peripheral or slave device to seamlessly transition in and out of sleep state while remaining completely transparent to host software. When the device is in a sleep mode and incoming data is detected, the device begins a wake-up procedure and data is routed to a first, transitional memory. The size of the transitional memory is selected such that it is capable of buffering data received during time required for the system memory to stabilize from wake-up. Once a second, extended memory is stabilized, the data is buffered from the transitional memory to the extended memory. The device resumes normal operation when its processor has initialized and can read data from the extended memory.

Abstract: Systems and methods disclosed herein receive a network application proxy (NAP)-extended API function call issued by a networking-aware host application. The NAP-extended API function call provides parameter values associated with a host off-loadable packet exchange sequence. Using the parameter values, a NAP module intercepts and responds to one or more incoming network packets associated with the host off-loadable packet exchange sequence while the host processor is in a sleep mode state or is transitioning between sleep mode states.

Abstract: A device with an autonomous sleep characteristic, which is in communication with a host, is described. The device includes one or more communication subsystems. Each communication subsystem maintains a sleep activity indicator that indicates whether a corresponding communication subsystem is allowed to go to sleep. Each communication subsystem can autonomously enter a sleep state, when its sleep activity indicator indicates that the corresponding communication subsystem is, in fact, allowed to go to sleep. The device also includes a controller. The controller has a block memory which stores data written to the device from the host. The controller further includes a sleep state indicator that indicates a sleep state of each communication subsystem.

Abstract: A wireless universal serial bus (USB) system that includes a wireless USB host, a first wireless USB device, and a second wireless USB device. The wireless USB host is configured to wirelessly transmit a beacon over a wireless USB network based on a wireless USB protocol. The first and second wireless USB devices are configured to exchange wireless packets with the wireless USB host. The beacon designates the wireless USB network address access times for the first and second wireless USB devices.

Abstract: A dual platform communication controller, a method of controlling communication of data packets based on different communication standards and a wireless transceiver. In one embodiment, the dual platform communication controller includes: (1) a signal interpreter configured to recognize first data packets based on a first communication standard and second data packets based on a second communication standard and (2) a traffic manager coupled to the signal interpreter and configured to dynamically control communication of the second data packets including active second data packets and allocate bandwidth for communication of the first and second data packets.