Abstract: A novel and useful neural network (NN) processing core adapted to implement artificial neural networks (ANNs) and incorporating strictly separate control and data planes. The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level. Dynamic resource assignment agility is provided which can be adjusted as required depending on resource availability and capacity of the device.

Abstract: Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The various mechanisms of the present invention address ANN system level safety in situ, as a system level strategy that is tightly coupled with the processor architecture. The NN processor incorporates several functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well.

Abstract: Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The various mechanisms of the present invention address ANN system level safety in situ, as a system level strategy that is tightly coupled with the processor architecture. The NN processor incorporates several functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well.

Abstract: A novel and useful augmented artificial neural network (ANN) incorporating an existing artificial neural network (ANN) coupled to a supplemental ANN and a first-in first-out (FIFO) stack for storing historical output values of the network. The augmented ANN exploits the redundant nature of information present in an input data stream. The addition of the supplemental ANN along with a FIFO enables the augmented network to look back into the past in making a decision for the current frame. It provides context aware object presence as well as lowers the rate of false detections and misdetections. The output of the existing ANN is stored in a FIFO to create a lookahead system in which both past output values of the supplemental ANN and ‘future’ values of the output of the existing ANN are used in making a decision for the current frame. In addition, the mechanism does not require retraining the entire neural network nor does it require data set labeling.

Abstract: A novel and useful system and method of input alignment for streamlining vector operations that reduce the required memory read bandwidth. The input aligner as deployed in the NN processor, functions to facilitate the reuse of data read from memory and to avoid having to re-read that data in the context of neural network calculations. The input aligner functions to distribute input data (or weights) to the appropriate compute elements while consuming input data in a single cycle. Thus, the input aligner is operative to lower the required read bandwidth of layer input in an ANN. This reflects the fact that normally in practice, a vector multiplication is performed every time instance. This considers the fact that in many native calculations that take place in an ANN, the same data point is involved in multiple calculations.

Abstract: Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The various mechanisms of the present invention address ANN system level safety in situ, as a system level strategy that is tightly coupled with the processor architecture. The NN processor incorporates several functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well.

Abstract: A novel and useful neural network (NN) processing core adapted to implement artificial neural networks (ANNs). The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level. Dynamic resource assignment agility is provided which can be adjusted as required depending on resource availability and capacity of the device.

Abstract: A Wi-Fi device includes a controller coupled to a writeable memory implementing a MAC and PHY layer and to a transceiver. Connection data stored in the writeable memory includes Wi-Fi connection parameters including ?1 router MAC level information or a most recently utilized (MRU) channel used, and IP addresses including ?1 of an IP address of the Wi-Fi device, IP address of the MRU router, an IP address of a MRU target server, and an IP address of a network connected device. An accelerated reconnecting to a Wi-Fi network algorithm is implemented by the processor is for starting from being in a network disconnected state, establishing current connection parameters for a current Wi-Fi network connection using the Wi-Fi connection parameters for at least one MAC layer parameter for the MAC layer.

Abstract: A Wi-Fi device includes a controller coupled to a writeable memory implementing a MAC and PHY layer and to a transceiver. Connection data stored in the writeable memory includes Wi-Fi connection parameters including ?1 router MAC level information or a most recently utilized (MRU) channel used, and IP addresses including ?1 of an IP address of the Wi-Fi device, IP address of the MRU router, an IP address of a MRU target server, and an IP address of a network connected device. An accelerated reconnecting to a Wi-Fi network algorithm is implemented by the processor is for starting from being in a network disconnected state, establishing current connection parameters for a current Wi-Fi network connection using the Wi-Fi connection parameters for at least one MAC layer parameter for the MAC layer.

Abstract: In a described example, an integrated circuit includes an input coupled to receive a plurality of beacon frames, the beacon frames include an indication of data transmissions available for a device that includes the integrated circuit. The integrated circuit also includes a controller configured to compare the plurality of beacon frames to determine a plurality of bytes prior to the indication of data transmission available that is present in each of the plurality of beacon frames and is configured to provide a signal indicating a low power mode in which the device does not receive transmissions and to provide a signal indicating a wake mode at a selected time before transmission of the plurality of bytes in a subsequent beacon transmission.

Abstract: A novel and useful system and method of improved power performance and lowered memory requirements for an artificial neural network based on packing memory utilizing several structured sparsity mechanisms. The invention applies to neural network (NN) processing engines adapted to implement mechanisms to search for structured sparsity in weights and activations, resulting in a considerably reduced memory usage. The sparsity guided training mechanism synthesizes and generates structured sparsity weights A compiler mechanism within a software development kit (SDK), manipulates structured weight domain sparsity to generate a sparse set of static weights for the NN. The structured sparsity static weights are loaded into the NN after compilation and utilized by both the structured weight domain sparsity mechanism and the structured activation domain sparsity mechanism.

Abstract: A novel and useful system and method of improved power performance and lowered memory requirements for an artificial neural network based on packing memory utilizing several structured sparsity mechanisms. The invention applies to neural network (NN) processing engines adapted to implement mechanisms to search for structured sparsity in weights and activations, resulting in a considerably reduced memory usage. The sparsity guided training mechanism synthesizes and generates structured sparsity weights A compiler mechanism within a software development kit (SDK), manipulates structured weight domain sparsity to generate a sparse set of static weights for the NN. The structured sparsity static weights are loaded into the NN after compilation and utilized by both the structured weight domain sparsity mechanism and the structured activation domain sparsity mechanism.

Abstract: A novel and useful system and method of improved power performance and lowered memory requirements for an artificial neural network based on packing memory utilizing several structured sparsity mechanisms. The invention applies to neural network (NN) processing engines adapted to implement mechanisms to search for structured sparsity in weights and activations, resulting in a considerably reduced memory usage. The sparsity guided training mechanism synthesizes and generates structured sparsity weights A compiler mechanism within a software development kit (SDK), manipulates structured weight domain sparsity to generate a sparse set of static weights for the NN. The structured sparsity static weights are loaded into the NN after compilation and utilized by both the structured weight domain sparsity mechanism and the structured activation domain sparsity mechanism.

Abstract: A novel and useful system and method of improved power performance and lowered memory requirements for an artificial neural network based on packing memory utilizing several structured sparsity mechanisms. The invention applies to neural network (NN) processing engines adapted to implement mechanisms to search for structured sparsity in weights and activations, resulting in a considerably reduced memory usage. The sparsity guided training mechanism synthesizes and generates structured sparsity weights A compiler mechanism within a software development kit (SDK), manipulates structured weight domain sparsity to generate a sparse set of static weights for the NN. The structured sparsity static weights are loaded into the NN after compilation and utilized by both the structured weight domain sparsity mechanism and the structured activation domain sparsity mechanism.

Abstract: In a described example, an integrated circuit includes an input coupled to receive a plurality of beacon frames, the beacon frames include an indication of data transmissions available for a device that includes the integrated circuit. The integrated circuit also includes a controller configured to compare the plurality of beacon frames to determine a plurality of bytes prior to the indication of data transmission available that is present in each of the plurality of beacon frames and is configured to provide a signal indicating a low power mode in which the device does not receive transmissions and to provide a signal indicating a wake mode at a selected time before transmission of the plurality of bytes in a subsequent beacon transmission.

Abstract: A novel and useful system and method of input alignment for streamlining vector operations that reduce the required memory read bandwidth. The input aligner as deployed in the NN processor, functions to facilitate the reuse of data read from memory and to avoid having to re-read that data in the context of neural network calculations. The input aligner functions to distribute input data (or weights) to the appropriate compute elements while consuming input data in a single cycle. Thus, the input aligner is operative to lower the required read bandwidth of layer input in an ANN. This reflects the fact that normally in practice, a vector multiplication is performed every time instance. This considers the fact that in many native calculations that take place in an ANN, the same data point is involved in multiple calculations.

Abstract: A novel and useful artificial neural network that incorporates emphasis and focus techniques to extract more information from one or more portions of an input image compared to the rest of the image. The ANN recognizes that valuable information in an input image is typically not distributed throughout the image but rather is concentrated in one or more regions. Rather than implement CNN layers sequentially (i.e. row by row) on the input domain of each layer, the present invention leverages the fact that valuable information is focused in one or more regions of the image where it is desirable to apply more attention and for which it is desired to apply more elaborate evaluation. Precision dilution can be applied to those portions of the input image that are not the center of focus and emphasis. A spatial aware function determines the location(s) of the ears of focus and is applied to the first convolutional layer.

Abstract: A Wi-Fi device includes a controller coupled to a writeable memory implementing a MAC and PHY layer and to a transceiver. Connection data stored in the writeable memory includes Wi-Fi connection parameters including ?1 router MAC level information or a most recently utilized (MRU) channel used, and IP addresses including ?1 of an IP address of the Wi-Fi device, IP address of the MRU router, an IP address of a MRU target server, and an IP address of a network connected device. An accelerated reconnecting to a Wi-Fi network algorithm is implemented by the processor is for starting from being in a network disconnected state, establishing current connection parameters for a current Wi-Fi network connection using the Wi-Fi connection parameters for at least one MAC layer parameter for the MAC layer.

Abstract: A novel and useful artificial neural network that incorporates emphasis and focus techniques to extract more information from one or more portions of an input image compared to the rest of the image. The ANN recognizes that valuable information in an input image is typically not distributed throughout the image but rather is concentrated in one or more regions. Rather than implement CNN layers sequentially (i.e. row by row) on the input domain of each layer, the present invention leverages the fact that valuable information is focused in one or more regions of the image where it is desirable to apply more attention and for which it is desired to apply more elaborate evaluation. Precision dilution can be applied to those portions of the input image that are not the center of focus and emphasis. A spatial aware function determines the location(s) of the ears of focus and is applied to the first convolutional layer.

Abstract: A novel and useful neural network (NN) processing core adapted to implement artificial neural networks (ANNs). The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level. Dynamic resource assignment agility is provided which can be adjusted as required depending on resource availability and capacity of the device.