Patents by Inventor Avner Badihi

Avner Badihi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Illumination apparatus confining light by total internal reflection and methods of forming the same
    Patent number: 8591072
    Abstract: In various embodiments, an illumination apparatus includes an air gap between a sub-assembly and a waveguide attached thereto at a plurality of discrete attachment points, as well as a bare-die light-emitting diode encapsulated by the waveguide.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: November 26, 2013
    Assignee: Oree, Inc.
    Inventors: Yosi Shani, Eran Fine, Baruch Schiffmann, Dafna Bortman Arbiv, Avner Badihi
  • ILLUMINATION APPARATUS CONFINING LIGHT BY TOTAL INTERNAL REFLECTION AND METHODS OF FORMING THE SAME
    Publication number: 20130121001
    Abstract: In various embodiments, an illumination apparatus includes an air gap between a sub-assembly and a waveguide attached thereto at a plurality of discrete attachment points, as well as a bare-die light-emitting diode encapsulated by the waveguide.
    Type: Application
    Filed: February 17, 2012
    Publication date: May 16, 2013
    Inventors: Yosi Shani, Eran Fine, Baruch Schiffmann, Dafna Bortman Arbiv, Avner Badihi
  • Packaged integrated circuits and methods of producing thereof
    Patent number: 7408249
    Abstract: A packaged integrated circuit and method for producing thereof, including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: August 5, 2008
    Assignee: Tessera Technologies Hungary Kft.
    Inventor: Avner Badihi
  • PACKAGED INTEGRATED CIRCUITS AND METHODS OF PRODUCING THEREOF
    Publication number: 20070013044
    Abstract: A packaged integrated circuit and method for producing thereof, including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface.
    Type: Application
    Filed: December 19, 2001
    Publication date: January 18, 2007
    Inventor: Avner Badihi
  • Packaged integrated circuits and methods of producing thereof
    Publication number: 20040183185
    Abstract: A packaged integrated circuit and method for producing thereof, including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface.
    Type: Application
    Filed: May 3, 2004
    Publication date: September 23, 2004
    Inventor: Avner Badihi
  • Method of making thin film surface mount fuses
    Patent number: 5228188
    Abstract: SMD fuses having consistent operating characteristics are fabricated by forming a repeating lithographic fuse element pattern on an insulative substrate, passivating the structure, bonding a protective glass plate over the passivation layer, slicing the assembly so formed, terminating the slices and cutting the slices into individual fuses. Fuses thus manufactured may be of any desired dimensions, including standard and non-standard chip sizes.
    Type: Grant
    Filed: July 24, 1992
    Date of Patent: July 20, 1993
    Assignee: AVX Corporation
    Inventors: Avner Badihi, Robert W. Franklin, Barry N. Breen
  • Thin film surface mount fuses
    Patent number: 5166656
    Abstract: SMD fuses having consistent operating characteristics are fabricated by forming a repeating lithographic fuse element pattern on an insulative substrate, passivating the structure, bonding a protective glass plate over the passivation layer, slicing the assembly so formed, terminating the slices and cutting the slices into individual fuses. Fuses thus manufactured may be of any desired dimensions, including standard and non-standard chip sizes.
    Type: Grant
    Filed: February 28, 1992
    Date of Patent: November 24, 1992
    Assignee: AVX Corporation
    Inventors: Avner Badihi, Robert W. Franklin, Barry N. Breen