Abstract: A method for the secured storing of a data element in an external memory, which is connected to a microcontroller via an interface module, which is configured to calculate memory addresses for data to be stored and for error correction values. The method includes receiving the data element to be stored by the interface module, a calculation by the interface module of a memory address in the external memory for the data element to be stored, and a writing, starting at the memory address, of the data element and of the error correction value via the interface module into the external memory, the error correction value immediately following the data element being written and the writing taking place within one addressing phase. A corresponding interface module, a corresponding microcontroller, and a corresponding control unit are also described.

Abstract: A method for the initial programming of a secondary computer. The method includes configuring a serial interprocessor interface between the secondary computer and a main computer, and data are written via the interface to a flash memory of the secondary computer.

Abstract: A control unit having a plurality of error shutdown interfaces by which, upon activation, in each case one or more components to be controlled by the control unit is/are able to be switched off. The control unit is set up to run one or more different applications, each of which is equipped to trigger an error shutdown if necessary, the control unit additionally being set up to provide internal interfaces for the one or more applications. The internal interfaces and the error shutdown interfaces are predefinably assignable to each other, so that in response to an invocation of one of the internal interfaces, the one or more error shutdown interfaces assigned to it is/are activated. A method for operation of the control unit is also described.

Abstract: An integrated circuit. The circuit includes a communication module including shared ports, and an error management module for managing at least one case of an error. The circuit is configured to communicate on multiple internal communication channels via the ports. The error management module includes at least one hardware path for selectively switching off the individual communication channels in the case of an error.

Abstract: A method updating a program in a flash memory includes executing a first image of the program while an address space of the program is imaged onto the memory blocks, which are operated in a single-level mode; copying part of the first image from a range within the address space, which is imaged onto one of the blocks, into a backup block; setting the one of the blocks to a multi-level mode; while the address range is imaged onto the backup block, programming the one of the blocks with part of the second image besides for the part of the first image; switching the address range back to the block while the block remains in the multi-level mode; as long as the second image is incomplete, repeating the copying, programming, and switching with further parts of the second image; and subsequently executing the second image instead of the first image.

Abstract: A computation unit having at least one computation core, a primary memory device, and at least one main connecting unit for connecting the at least one computation core to the primary memory device, the computation unit having at least two functional units, at least a first functional unit of the at least two functional units being embodied a) to receive first data from at least one further functional unit of the at least two functional units, and/or b) to transmit second data to at least one further functional unit of the at least two functional units.

Abstract: A method (10) for the initial programming of a secondary computer (22), characterized by the following features: —a serial interprocessor interface (21) between the secondary computer (22) and a main computer (23) is configured, and —the data (24) are written (12) via the interface (21) to a flash memory (25) of the secondary computer (22).

Abstract: A processing unit has a working memory. A direct memory access control unit includes a terminal connecting the direct memory access control unit to a bus system that connects the processing unit to the working memory and is configured to: read in, from at least two information blocks stored in the working memory and provided by the processing unit for transmission to a communication module connected to the bus system, pieces of control information characterizing respective priorities of the respective information blocks for the transmission to the communication module; ascertain a sequence for the transmission based on the respective priorities; and transmit the information blocks from the working memory to the communication module according to the ascertained sequence using a direct memory access from the working memory to the communication module.

Abstract: A method for synthesizing a circuit layout, characterized by the following features: primary circuit functions are placed on the circuit layout; secondary circuit functions are placed on the circuit layout; at least one first mask is generated in such a way that the first mask reproduces the primary circuit functions and covers the secondary circuit functions when a semiconductor substrate is structured according to the circuit layout by way of the first mask; and the placement of the circuit functions takes place in such a way that at least one changed mask reproduces the primary circuit functions and the secondary circuit functions when the semiconductor substrate is structured according to the circuit layout by way of at least one second mask.

Abstract: A method updating a program in a flash memory includes executing a first image of the program while an address space of the program is imaged onto the memory blocks, which are operated in a single-level mode; copying part of the first image from a range within the address space, which is imaged onto one of the blocks, into a backup block; setting the one of the blocks to a multi-level mode; while the address range is imaged onto the backup block, programming the one of the blocks with part of the second image besides for the part of the first image; switching the address range back to the block while the block remains in the multi-level mode; as long as the second image is incomplete, repeating the copying, programming, and switching with further parts of the second image; and subsequently executing the second image instead of the first image.

Abstract: A processing unit has a working memory. A direct memory access control unit includes a terminal connecting the direct memory access control unit to a bus system that connects the processing unit to the working memory and is configured to: read in, from at least two information blocks stored in the working memory and provided by the processing unit for transmission to a communication module connected to the bus system, pieces of control information characterizing respective priorities of the respective information blocks for the transmission to the communication module; ascertain a sequence for the transmission based on the respective priorities; and transmit the information blocks from the working memory to the communication module according to the ascertained sequence using a direct memory access from the working memory to the communication module.

Abstract: A computation unit having at least one computation core, a primary memory device, and at least one main connecting unit for connecting the at least one computation core to the primary memory device, the computation unit having at least two functional units, at least a first functional unit of the at least two functional units being embodied a) to receive first data from at least one further functional unit of the at least two functional units, and/or b) to transmit second data to at least one further functional unit of the at least two functional units.

Abstract: A model calculation unit for calculating a data-based function model in a control unit is provided, the model calculation unit having a processor core which includes: a multiplication unit for carrying out a multiplication on the hardware side; an addition unit for carrying out an addition on the hardware side; an exponential function unit for calculating an exponential function on the hardware side; a memory in the form of a configuration register for storing hyperparameters and node data of the data-based function model to be calculated; and a logic circuit for controlling, on the hardware side, the calculation sequence in the multiplication unit, the addition unit, the exponential function unit and the memory in order to ascertain the data-based function model.

Abstract: A method for updating a control device having a first processor core and having a first flash memory associated with the first processor core, in which the first processor core works with a first block of the first flash memory, in which while it is working, a second block, electronically separate from the first block, of the first flash memory is reprogrammed with a predefined memory image; and in which after reprogramming, the first processor core is switched over from the first block of the first flash memory to the second block of the first flash memory.

Abstract: An integrated circuit, preferably for controlling vehicle functions, having an analog-digital converter for converting an analog signal into digital measurement values, a DSP unit, connected downstream from the analog-digital converter, for pre-processing the digital measurement values, a central computing unit, connected to the DSP unit so as to transmit data, for further processing of the digital measurement values, the DSP unit being set up to control the analog-digital converter during operation.

Abstract: A direct memory access control device for at least one computing unit includes a terminal for connecting the direct memory access control device to a bus system that connects the computing unit to a working memory, and processing circuitry configured to read out, from a source module connected to the bus system, first data of at least one information block stored at least temporarily in the source module, ascertain a target address in the working memory for the at least one information block as a function of the first data and of configuration information, and transmit the at least one information block from the source module to the target address using a direct memory access by the source module to the working memory.

Abstract: A microcontroller for a control unit, in particular for a vehicle control unit, includes a central processing unit (CPU), at least one interface-unspecific input module, at least one interface-unspecific output module, at least one routing unit and at least one arithmetic unit for processing interface-specific information. The microcontroller is configurable in such a way that the at least one interface-unspecific input module, the at least one interface-unspecific output module, the at least one routing unit and the at least one arithmetic unit for processing interface-specific information fulfill functions corresponding to one of multiple serial interfaces, in particular of SPI, UART, LIN, CAN, PSI5, FlexRay, SENT, IC2, MSC or Ethernet.

Abstract: A method for carrying out a refresh of a memory area of a non-volatile memory unit of an embedded system includes refreshing the memory area when a refresh-triggering criterion is satisfied, a check being performed at predefined time intervals to determine whether the refresh-triggering criterion is satisfied, the embedded system being automatically activated and the check being performed if the embedded system is deactivated following the expiration of any of the predefined time intervals.

Abstract: A method for performing a refresh of a first memory area of a non-volatile memory unit includes overwriting at least one additional memory area of the non-volatile memory unit with a memory content from the first memory area, adding a reference to the at least one additional memory area to a memory address area corresponding to the memory content and removing a reference to the first memory area from the memory address area corresponding to the memory content, overwriting the first memory area with the memory content from the at least one additional memory area, and subsequently replacing the reference in the memory address area with the reference to the first memory area.

Abstract: A control device in a vehicle includes a unit for calculating, during operation of the vehicle, on the basis of at least one input variable ascertained during operation, at least one output variable for a control system of functions of the vehicle. The control device performs the calculation of the output variables using a Bayesian regression of training values ascertained, before operation, for the output variable and the input variable.