Abstract: A device having a processor and a memory element positioned outside the processor, as well as a device for linking a memory element to a processor, and a memory element, are described, the processor and the memory element being linked via address and/or data lines, the address and/or data lines each being implemented in a structure combining a differential structure, LVDS in particular, and a structure having transistors which switch to ground and voltage, SSTL in particular, which has corresponding transmitters and receivers.

Abstract: A method and a device for detecting at least one first signal for a computer is described, having a converter device which converts the first signal to a second signal, and including a reference device to which a first reference signal is applied and which converts it to a second reference signal. Also included is a first switching element which can switch the second reference signal to the converter device, the converter device converting the second reference signal to a third reference signal. The method and device described herein also include a matching arrangement, which also receives the second reference signal and matches the second reference signal to a fourth reference signal, and at least a second switching element which can switch the fourth reference signal to the converter device, which then converts it to a fifth reference signal.

Abstract: A memory arrangement is provided, which has a programmable memory and a first buffer memory associated with the programmable memory, to which buffer memory, in the case of a command access, at least one command following the accessed command is written. A second buffer memory may also be provided, to which buffer memory, in the case of a data access, at least one datum following the accessed datum is written. Also provided is a method for reading from a memory arrangement during program execution, wherein presence of a command access or a data access recognized, and a command following the accessed command is written to a first buffer memory and a datum following the accessed datum is written to a second buffer memory. Thus, in this manner, a separate buffer memory is described for data accesses, and thus the content of the buffer for command accesses is not overwritten or destroyed when data accesses occur during the program execution.

Abstract: A memory element and a device having a processor and a memory element, the memory element being positioned outside of the processor and being connectible to a processor via address and/or data lines, the address and/or data lines are each configured in an LVDS structure having corresponding drivers and receivers, and the drivers and receivers each being integrated in the memory element or in the processor.

Abstract: A method and a device for refreshing the memory content of at least one memory cell of a read-only memory is described. An embodiment of the present invention involves determining the instantaneous charge status of the memory cell; comparing the instantaneous charge status of the memory cell with a charge threshold (U_schw) which is greater than the reading charge (U_erh) sufficient for correct detection of the memory content of the memory cell; and raising the charge status of the memory cell if the instantaneous charge status of the memory cell is below the charge threshold (U_schw).

Abstract: A method of testing and/or monitoring the system frequency of a microcontroller, in which the working frequency of a voltage-regulated oscillator or VCO, which is in an operative connection with the microcontroller, is measured, and the system frequency being determined and/or checked on the basis of the measured working voltage.

Abstract: A method and a device for detecting at least one first signal for a computer is described, having a converter device which converts the first signal to a second signal, and including a reference device to which a first reference signal is applied and which converts it to a second reference signal. Also included is a first switching element which can switch the second reference signal to the converter device, the converter device converting the second reference signal to a third reference signal. The method and device described herein also include a matching arrangement, which also receives the second reference signal and matches the second reference signal to a fourth reference signal, and at least a second switching element which can switch the fourth reference signal to the converter device, which then converts it to a fifth reference signal.

Abstract: A method and a device having a processor module for controlling operating sequences, in particular in an engine control unit in a motor vehicle, peripheral elements being selected by a processor module having a predetermined number of select interfaces by select signal output over these select interfaces, and instructions being transmitted to the peripheral elements over at least one information interface of the processor module. Selection identifiers are assigned to the instructions and transmitted together with them. Thus, a selection of peripheral elements is made by a select signal and a selection identifier.

Abstract: A method is described for storing and processing/filtering signals, as well as a memory arrangement, a signal processing arrangement and, in particular, a digital filter arrangement having a plurality of filter modules for digital processing/filtering of input values, having a memory area and a signal processing module, which contains in particular at least one multiplier-accumulator which has at least one multiplier and at least one adder. The input values, coefficients, and output values of the arrangement can be stored in the memory area and called up again therefrom as needed. The input values are gated with the coefficients to form output values. In order to alleviate the load on a higher-level microprocessor by digital processing/filtering of the input values, it is proposed that the digital filter arrangement have a Direct Memory Access controller for coordinating data transmission of the filter coefficients, input values and output values between the multiplier-accumulator and the memory area.

Abstract: A method of detecting manipulation of a programable memory device of a digital controller for a motor vehicle is described; data and control programs for operation of the controller and for control/regulation of certain functions of the motor vehicle can be stored in the memory device. To permit especially reliable detection of manipulation in the simplest possible way, in conjunction with each programing/reprograming operation of the programable memory device, information regarding the programing/reprograming operation is stored in a separate memory area of the memory device where only reading and programing are possible, and in order to detect manipulation, the content of the separate memory area is read out and compared with given information.

Abstract: A method for protecting a microcomputer system against manipulation of data stored in a storage arrangement of the microcomputer system, in particular for protecting a program stored in the storage arrangement. The microcomputer system includes a microcomputer assigned to the storage arrangement, the microcomputer accessing the storage arrangement for the purpose of processing the data, i.e., the program.

Abstract: A method for activating a microprocessor, which is part of a microcontroller, within the framework of a boundary scan test procedure according to Institute of Electrical and Electronic Engineers (IEEE) standard 1149, using a Joint European Test Action Group (JTAG) interface of the microprocessor. To be able to test a microcontroller, using the boundary scan test procedure, even when the JTAG interface is not accessible by a separate hardware adaptor of a JTAG tester, it is proposed that the JTAG interface of the microprocessor be activated by a test routine executable on the microprocessor.

Abstract: A method and a device for refreshing the memory content of at least one memory cell of a read-only memory is described. An embodiment of the present invention involves determining the instantaneous charge status of the memory cell; comparing the instantaneous charge status of the memory cell with a charge threshold (U_schw) which is greater than the reading charge (U_erh) sufficient for correct detection of the memory content of the memory cell; and raising the charge status of the memory cell if the instantaneous charge status of the memory cell is below the charge threshold (U_schw).