Abstract: In described examples, a method of operating a transceiver with a transmitter and a receiver includes generating a frequency reference. In the transmitter: A phase locked loop (PLL) generates a first voltage controlled oscillator (VCO) control voltage responsive to the frequency reference. A VCO in the transmitter generates a transmitter VCO signal responsive to the first VCO control voltage, and the PLL is locked to the transmitter VCO signal. In the receiver: A signal is received. A receiver VCO generates a receiver VCO signal responsive to the first or a second VCO control voltage. The receiver VCO signal is multiplied by the received signal to generate an I component, and by the received signal phase shifted by 90° to generate a Q component. The second VCO control signal is generated responsive to the I component and the Q component.

Abstract: An interposer acts as a buffer zone between a transceiver IC and a dielectric waveguide interconnect and establishes two well-defined reference planes that can be optimized independently. The interposer includes a block of material having: a first interface region to interface with an antenna coupled to an integrated circuit (IC); and a second interface region to interface to the dielectric waveguide. An interface waveguide is formed by a defined region positioned within the block of material between the first interface region and the second interface region.

Abstract: A multi-die module includes a first die with a first electronic device and a second die with a second electronic device. The multi-die module also includes a contactless coupler configured to convey signals between the first electronic device and the second electronic device. The multi-die module also includes a coupling loss reduction structure.

Abstract: In described examples, a method of operating a transmitter includes generating a frequency reference signal having a reference frequency and outputting the frequency reference to a phase locked loop (PLL) that includes a voltage controlled oscillator (VCO). The VCO output is locked to the frequency reference signal to form a carrier signal. The transmitter receives an I input signal, a Q input signal, and a direct current (DC) leaky carrier signal. Either the I input signal or the Q input signal is added to the leaky carrier signal. The carrier signal is modulated with the resulting two signals using an I-Q mixer to generate a modulated signal that includes an unmodulated carrier signal component. The modulated signal is then transmitted.

Abstract: A track and hold circuit includes a signal input terminal, a clock input terminal, an output terminal, a transistor, and a bootstrapping circuit with a transformer. The transistor includes a source, a drain, and a gate, where the source is coupled to the signal input terminal, and the drain is coupled to the output terminal. The transformer includes a primary winding coupled to the clock input terminal, and a secondary winding. The secondary winding is coupled between the source and the gate to control a gate-source voltage of the transistor.

Abstract: A multi-die module includes a first die with a first device and a second die with a second device. The multi-die module also includes a contactless coupler configured to convey signals between the first device and the second device. The multi-die module also includes a coupling loss reduction structure.

Abstract: A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

Abstract: An interposer that acts as a buffer zone between a transceiver IC and a dielectric waveguide interconnect is used to establish two well defined reference planes that can be optimized independently. The interposer includes a block of material having a first interface region to interface with an antenna coupled to an integrated circuit (IC) and a second interface region to interface to the dielectric waveguide. An interface waveguide is formed by a defined region positioned within the block of material between the first interface region and the second interface region.

Abstract: A multi-die module includes a first die with a first substrate and a first device formed over the first substrate, wherein the first substrate includes a cavity on a side opposite the first device. The multi-die module also includes a second die with a second substrate and a second device formed over the second substrate, wherein the second die is positioned at least partially in the cavity. The multi-die module also includes a coupler configured to convey signals between the first device and the second device.

Abstract: A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

Abstract: In described examples, a ring oscillator includes a series of N stages in a first ring. Each stage includes a respective output terminal coupled to a respective input terminal of a next one of the stages in the first ring. N is a positive odd-numbered integer of at least three. A series of N level shifters in a second ring are respectively connected to the N stages. Each level shifter receives a respective clock output from a respective output terminal of a stage to which it is connected and generates a respective boosted clock output in response thereto. The boosted clock output is coupled to control an impedance state of a next one of the level shifters in the second ring.

Abstract: A clock generator includes a hermetically sealed cavity and clock generation circuitry. A dipolar molecule that exhibits a quantum rotational state transition at a fixed frequency is disposed in the cavity. The clock generation circuitry is configured to generate an output clock signal based on the fixed frequency of the dipolar molecule. The clock generation circuitry includes a detector circuit, a multiplier, and reference oscillator control circuitry. The detector circuit is coupled to the cavity, and is configured to generate a detection signal representative of an amplitude of a signal at an output of the cavity. The multiplier is coupled to the detector circuit, and is configured to multiply the detection signal with a mixing signal to produce a derivative of the detection signal. The reference oscillator control circuitry is configured to set a frequency of a reference oscillator based on the derivative of the detection signal.

Abstract: In described examples, a ring oscillator includes a series of N stages in a first ring. Each stage includes a respective output terminal coupled to a respective input terminal of a next one of the stages in the first ring. N is a positive odd-numbered integer of at least three. A series of N level shifters in a second ring are respectively connected to the N stages. Each level shifter receives a respective clock output from a respective output terminal of a stage to which it is connected and generates a respective boosted clock output in response thereto. The boosted clock output is coupled to control an impedance state of a next one of the level shifters in the second ring.

Abstract: A pulsed light source illuminates a scene with a virtual array of points. Light reflected by the scene is detected by a small pixel array, allowing generation of a three-dimensional map of the scene. A processing element processing data output by the small pixel array uses a multipath resolution algorithm to resolve individual objects in the scene.

Abstract: A voltage sensor device includes an oscillator unit, the oscillator unit having a tunable bulk acoustic wave (BAW) resonator device and an oscillator core. The voltage sensor device also includes a frequency analyzer configured to obtain frequency measurements for the oscillator unit and to determine a voltage sense value based on a comparison of at least some of the obtained frequency measurements. The voltage sensor device also includes an output interface configured to store or output voltage sense values determined by the frequency analyzer.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to provide phase imbalance correction. An example system includes a phase detector to obtain a first signal and generate a first output, a comparator coupled to the phase detector, the comparator to generate a second output based on the first output, and an amplifier coupled to the comparator, the amplifier to adjust a first phase response of the first signal based on the second output.

Abstract: An optical position sensing system is disclosed. The system includes a substrate having a surface. A plurality of photodetectors are at multiple locations across the surface, each of the plurality of photodetectors providing detector pulse signals in response to receiving the light. The system further includes a processor that determines a phase shift between the transmitted light pulse signals and the respective detector pulse signals and applies a multi-path resolution operation to distinguish between the detector pulse signals representing the transmitted light pulse signals and those representing reflected light pulse signals. The processor also calculates a distance of a transmitting device from each of the photodetectors based on the determined phase shift and the multi-path resolution operation and calculates a multi-dimensional position of the transmitting device relative to the substrate based on the calculated distances.

Abstract: A multi-die module includes a first die with a first device and a second die with a second device. The multi-die module also includes a contactless coupler configured to convey signals between the first device and the second device. The multi-die module also includes a coupling loss reduction structure.

Abstract: A multi-die module includes a first die with a first substrate and a first device formed over the first substrate, wherein the first substrate includes a cavity on a side opposite the first device. The multi-die module also includes a second die with a second substrate and a second device formed over the second substrate, wherein the second die is positioned at least partially in the cavity. The multi-die module also includes a coupler configured to convey signals between the first device and the second device.

Abstract: An ultrasonic detection circuit includes a transmitter circuit that provides excitation signals to an ultrasonic transducer during an excitation interval. A control circuit includes a port to receive a command. The control circuit controls the frequency and the duty cycle of the excitation signals of the transmitter circuit during the excitation interval. The control circuit generates a first excitation signal sequence of the excitation interval followed by a first monitoring period to receive a first echo signal in response to the command. The control circuit generates a second excitation signal sequence of the excitation interval followed by a second monitoring period to receive a second echo signal in response to the command. The control circuit outputs results via the port based on at least one of the first or second echo signals received.