Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

Abstract: A wide band, wide operating range, general purpose digital phase locked loop (PLL) runs in the digital domain except for the associated Time Digitizer (T2D) and Digitally-Controlled-Oscillator (DCO). By calibrating the T2D and DCO on the fly, a constant PLL loop BW is achieved by using the calibrated Phase Frequency Detection (PFD) and DCO information to normalize the control loop correction regardless of the input clock frequency, power supply voltage, processing and temperature variations. PLL loop BW is completely decoupled from the operating conditions and semiconductor device variation. This means that the PLL loop BW can be chosen very aggressively to reject the noise, thus achieving a low jitter, high performance PLL. Furthermore, since this PLL can reliably operate over a wide operating range, it is a one-design-fits-all general purpose PLL.

Abstract: A symmetric glitch free clock multiplexing circuit allows the input clock to a digital or analog processing unit to be switched from one frequency to the other at any moment during the operation, assuming the respective clocks themselves are stable. There exist no restrictions on the clocks or the switch control signal to be synchronous in any fashion. This circuit guarantees a glitch free output and also prevents short cycling of the output clock. Since all the related clocks and switch control signal are asynchronous, this circuit further eliminates meta-stability problems. Its symmetrical architecture allows the circuit to function with the output clock being switched from slow clock to fast clock and vise versa.

Abstract: A high PSRR, low power semiconductor digitally controlled oscillator (DCO) architecture employs only one simple current steering D/A converter directly on top of a multi-stage current controlled oscillator. The architecture provides a good building block for many circuit applications, e.g., all digital phase lock loops, direct modulation transmitters for wireless devices, and the like.

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract: Sigma delta modulators and digital to analog converters therefor are disclosed, in which intentional mismatch is provided in circuit elements of the digital to analog converter to facilitate tone reduction where dynamic element matching is used in selecting the digital to analog converter circuit elements. Methods are disclosed for fabricating digital to analog converters for providing analog feedback using a group of circuit elements selected according to a quantized output signal in a sigma delta modulator, in which a plurality of matched circuit elements having values within a tolerance amount of a design value are provided in the group along with at least one mismatched circuit element having a mismatched element value differing from the design value by a mismatch amount, where the mismatch amount is greater than the tolerance amount.

Abstract: A non-linear time digitizer delay chain and a respective lookup table for converting the phase error into a digital code together prevent a phase error pulse from saturating the delay chain, even when the input frequency varies by orders of magnitude. By using a non-linear T2D delay chain along with a corresponding lookup table, the phase error pulse associated with a digital phase lock loop (PLL) can be measured and represented in more meaningful and accurate ways that that achievable when using a conventional T2d circuit to convert the phase error into a digital code. The lookup table implementation allows an additional degree of freedom for designers to apply a transfer function to the digital code measured by the T2D.

Abstract: A high PSRR, low power semiconductor digitally controlled oscillator (DCO) architecture employs only one simple current steering D/A converter directly on top of a multi-stage current controlled oscillator. The architecture provides a good building block for many circuit applications, e.g., all digital phase lock loops, direct modulation transmitters for wireless devices, and the like.

Abstract: A wide band, wide operating range, general purpose digital phase locked loop (PLL) runs in the digital domain except for the associated Time Digitizer (T2D) and Digitally-Controlled-Oscillator (DCO). By calibrating the T2D and DCO on the fly, a constant PLL loop BW is achieved by using the calibrated Phase Frequency Detection (PFD) and DCO information to normalize the control loop correction regardless of the input clock frequency, power supply voltage, processing and temperature variations. PLL loop BW is completely decoupled from the operating conditions and semiconductor device variation. This means that the PLL loop BW can be chosen very aggressively to reject the noise, thus achieving a low jitter, high performance PLL. Furthermore, since this PLL can reliably operate over a wide operating range, it is a one-design-fits-all general purpose PLL.

Abstract: A symmetric glitch free clock multiplexing circuit allows the input clock to a digital or analog processing unit to be switched from one frequency to the other at any moment during the operation, assuming the respective clocks themselves are stable. There exist no restrictions on the clocks or the switch control signal to be synchronous in any fashion. This circuit guarantees a glitch free output and also prevents short cycling of the output clock. Since all the related clocks and switch control signal are asynchronous, this circuit further eliminates meta-stability problems. Its symmetrical architecture allows the circuit to function with the output clock being switched from slow clock to fast clock and vise versa.

Abstract: An analog signal (VIN) is converted into a digital signal (24) by sampling the analog signal at a plurality of points in time to produce a sampled signal (32) which represents the analog signal. A filtering operation is advantageously incorporated into the sampling operation (102). The filtering operation filters the analog signal such that the sampled signal represents a filtered version of the analog signal. The digital signal is produced from the sampled signal.

Abstract: A flash analog-to-digital converter having precise differential voltage interpolation without the use of silicide-blocked resistors. A reference conversion voltage output portion converts an analog input voltage on the basis of a plurality of reference voltages into a plurality of reference conversion voltages. An intermediate voltage generating portion includes a predetermined number of non-linear resistance units respectively provided between one voltage and the other voltage in pairs of a predetermined number of the plurality of reference conversion voltages to generate a plurality of intermediate voltages by resistance division using the predetermined number of non-linear resistance units. In addition, the intermediate voltage generating portion generates a plurality of conversion voltages. A digital data output portion outputs the digital output voltage on the basis of the plurality of conversion voltages using double interpolation.

Abstract: A system for handling a power supply interruption in a non-volatile memory (10) is disclosed that includes a status indicator set (20) for each sector (16) of a non-volatile memory array (14). The status indicator set (20) is operable to indicate a status for the sector (16) and is independently erasable from the sector (16). A state machine (30) is operable to perform operations on the sectors (16). The state machine (30) is also operable to adjust the status indicator set (20) for a sector (16) prior to performing an operation on the sector (16) to indicate an interruption status and to adjust the status indicator set (20) for the sector (16) after completing the operation to indicate a completed status. Status indicator set (20) preferably includes alternatively employed active indicator sub-sets and erase indicator sub-sets.

Abstract: A flash analog-to-digital converter having precise differential voltage interpolation without the use of silicide-blocked resistors. A reference conversion voltage output portion converts an analog input voltage on the basis of a plurality of reference voltages into a plurality of reference conversion voltages. An intermediate voltage generating portion includes a predetermined number of non-linear resistance units respectively provided between one voltage and the other voltage in pairs of a predetermined number of the plurality of reference conversion voltages to generate a plurality of intermediate voltages by resistance division using the predetermined number of non-linear resistance units. In addition, the intermediate voltage generating portion generates a plurality of conversion voltages. A digital data output portion outputs the digital output voltage on the basis of the plurality of conversion voltages using double interpolation.

Abstract: A system for storing data in read-only memory is disclosed that comprises bit level conductors, transistors, and sets of reference level conductors. Each reference level conductor has a reference value. A selected reference level conductor transmits a selected reference value to one of the transistors. The transistor transmits the selected reference value to a selected bit level conductor having a selected bit value. The bit level conductors, the transistors and the reference level conductors store data by encoding data as a combination comprising the selected bit value and the selected reference value. A method for storing data in read-only memory is disclosed. Bit level conductors having bit values, transistors, and sets of reference level conductors having reference values are provided. A selected bit value of a selected bit level conductor and a selected reference value of a selected reference level conductor are selected.

Abstract: A capacitor includes a first conductive layer disposed outwardly from a semiconductor substrate and comprising a first plate and a second plate. The capacitor also includes a first via layer disposed outwardly from the first conductive layer and comprising a first via coupled to the first plate and a second via coupled to the second plate. The first and second vias are separated by a dielectric and are operable to be charged with different potentials to establish a capacitance between the first and second vias. The capacitor further includes a second conductive layer disposed outwardly from the first via layer and comprising a third plate coupled to the first via and a fourth plate coupled to the second via.

Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract: An analog signal (VIN) is converted into a digital signal (24) by sampling the analog signal at a plurality of points in time to produce a sampled signal (32) which represents the analog signal. A filtering operation is advantageously incorporated into the sampling operation (102). The filtering operation filters the analog signal such that the sampled signal represents a filtered version of the analog signal. The digital signal is produced from the sampled signal.