Patents by Inventor Baher S. Haroun
Baher S. Haroun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7962813Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.Type: GrantFiled: May 4, 2009Date of Patent: June 14, 2011Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Baher S. Haroun, Brian J. Lasher, Anjali Kinra
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Publication number: 20110084864Abstract: An embodiment of the invention provides a single-ended polar transmitting circuit. The single-ended polar transmitting circuit comprises a DAC, a differential-to-single-ended converter, a GmC filter and a load. The GmC filter comprises two gain stages, two filters, two switching devices, a translinear loop and a current mirror. When a second clock signal is high, a first current is conducted through the load, a second switching device and a second gain stage. When a first clock signal is high, a second current is conducted through a first switching device and the second gain stage. The first gain stage has a transconductance Gm1 and the second gain stage has a transconductance Gm2. The bandwidth of the GmC filter is approximately equal to the square root of the quantity (Gm1*Gm2)/(C1*C2). The bandwidth of the GmC filter is substantially a constant value.Type: ApplicationFiled: October 9, 2009Publication date: April 14, 2011Applicant: Texas Instruments IncorporatedInventors: Ganesh K. Balachandran, Baher S. Haroun
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Patent number: 7925942Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.Type: GrantFiled: August 11, 2009Date of Patent: April 12, 2011Assignee: Texas Instruments IncorporatedInventors: Baher S. Haroun, Lee D. Whetsel
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Patent number: 7919860Abstract: One aspect of the invention provides a semiconductor device that includes a microchip having an outermost surface. First and second bond pads are located on the microchip and near the outermost surface. A first UBM contact is located on the outermost surface and between the first and second bond pads. The first UBM contact is offset from the first bond pad. A second UBM contact is located on the outermost surface and between the first and second bond pads. The second UBM contact is offset from the second bond pad, and a capacitor supported by the microchip is located between the first and second UBM contacts.Type: GrantFiled: March 14, 2008Date of Patent: April 5, 2011Assignee: Texas Instruments IncorporatedInventors: Rajen M. Murugan, Robert F. McCarthy, Baher S. Haroun, Peter R. Harper
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Patent number: 7915905Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.Type: GrantFiled: April 16, 2010Date of Patent: March 29, 2011Assignee: Texas Instruments IncorporatedInventors: Baher S. Haroun, Gaurav Chandra, Vijaya Bhaskar Rentala, Venkatesh Srinivasan, Hisashi Shichijo, Krishnaswamy Nagaraj
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Publication number: 20100197053Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.Type: ApplicationFiled: April 16, 2010Publication date: August 5, 2010Inventors: Baher S. Haroun, Gaurav Chandra, Vijaya Bhaskar Rentala, Venkatesh Srinivasan, Hisashi Shichijo, Krishnaswamy Nagaraj
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Publication number: 20100162061Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.Type: ApplicationFiled: August 11, 2009Publication date: June 24, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Baher S. Haroun, Lee D. Whetsel
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Patent number: 7719299Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range.Type: GrantFiled: April 2, 2008Date of Patent: May 18, 2010Assignee: Texas Instruments IncorporatedInventors: Baher S. Haroun, Gaurav Chandra, Vijaya Bhaskar Rentala, Venkatesh Srinivasan, Hisashi Shichijo, Krishnaswamy Nagaraj
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Publication number: 20100099368Abstract: An FM-band transmit power amplifier and a method of transmitting in multiple bands. In one embodiment, the FM-band transmit power amplifier has an input and an output and includes: (1) a pre-filter including a charge-pump based integrator coupled to the input and a passive notch filter having a notch frequency in a band other than an FM band and (2) an output driver coupled between the passive pre-filter and the output and having PMOS and NMOS transconductors configured to receive an output from the passive filter.Type: ApplicationFiled: October 16, 2008Publication date: April 22, 2010Applicant: Texas Instruments IncorporatedInventors: Mehmet T. Ozgun, Baher S. Haroun
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Publication number: 20090265672Abstract: A method of designing an analog integrated circuit (IC), a parasitic constraint analyzer and a method of determining a layout of an analog IC complies with parasitic constraints. In one embodiment, the method of designing an analog IC includes: (1) creating a schematic of an analog integrated circuit based on a set of specifications, (2) attaching parasitic constraints to the schematic, (3) creating a layout of the analog integrated circuit based on the schematic including the parasitic constraints, (4) extracting parasitic values from parasitic elements of the layout and (5) comparing the extracted parasitic values with the parasitic constraints to verify compliance therewith.Type: ApplicationFiled: April 16, 2008Publication date: October 22, 2009Applicant: Texas Instruments IncorporatedInventors: Ian St.John, Mohamed Kamal Mahmoud, Baher S. Haroun
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Publication number: 20090251164Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range.Type: ApplicationFiled: April 2, 2008Publication date: October 8, 2009Inventors: Baher S. Haroun, Gaurav Chandra, Vijaya Bhaskar Rentala, Venkatesh Srinivasan, Hisashi Shichijo, Krishnaswamy Nagaraj
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Patent number: 7590910Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.Type: GrantFiled: March 27, 2007Date of Patent: September 15, 2009Assignee: Texas Instruments IncorporatedInventors: Baher S. Haroun, Lee D. Whetsel
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Publication number: 20090210188Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.Type: ApplicationFiled: May 4, 2009Publication date: August 20, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee D. Whetsel, Baher S. Haroun, Brian J. Lasher, Anjali Kinra
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Patent number: 7546502Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.Type: GrantFiled: May 8, 2008Date of Patent: June 9, 2009Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Baher S. Haroun, Brian J. Lasher, Anjali Kinra
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Publication number: 20090057889Abstract: One aspect of the invention provides a semiconductor device that includes a microchip having an outermost surface. First and second bond pads are located on the microchip and near the outermost surface. A first UBM contact is located on the outermost surface and between the first and second bond pads. The first UBM contact is offset from the first bond pad. A second UBM contact is located on the outermost surface and between the first and second bond pads. The second UBM contact is offset from the second bond pad, and a capacitor supported by the microchip is located between the first and second UBM contacts.Type: ApplicationFiled: March 14, 2008Publication date: March 5, 2009Applicant: Texas Instruments Inc.Inventors: Rajen M. Murugan, Robert F. McCarthy, Baher S. Haroun, Peter R. Harper
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Publication number: 20080215282Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.Type: ApplicationFiled: May 8, 2008Publication date: September 4, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee D. Whetsel, Baher S. Haroun, Brian J. Lasher, Anjali Kinra
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Patent number: 7389456Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.Type: GrantFiled: April 12, 2006Date of Patent: June 17, 2008Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Baher S. Haroun, Brian J. Lasher, Anjali Kinra
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Patent number: 7227404Abstract: A system and method are implemented for preventing regulated supply undershoot in state retained latches of a leakage controlled system, using a voltage source depending on a reference voltage that includes a decay to resolve undesirable undershoot.Type: GrantFiled: September 15, 2003Date of Patent: June 5, 2007Assignee: Texas Instruments IncorporatedInventors: Valerian Mayega, Baher S. Haroun
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Patent number: 7213171Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.Type: GrantFiled: February 4, 2004Date of Patent: May 1, 2007Assignee: Texas Instruments IncorporatedInventors: Baher S. Haroun, Lee D. Whetsel
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Patent number: 7129875Abstract: An analog-to-digital (A/D) converter system is provided that compensates for operating variations associated with one or more passive components of the A/D converter. In one aspect of the present invention, the A/D converter system comprises a sigma delta modulator having at least one passive component and a feedback path that includes at least one switched digital-to-analog converter (DAC), and a tracking reference generator that provides compensated reference signals to the at least one switched DAC for providing feedback to the sigma delta modulator. The compensated reference signals include inverse variations that cancel operating variations associated with the at least one passive component.Type: GrantFiled: July 8, 2005Date of Patent: October 31, 2006Assignee: Texas Instruments IncorporatedInventors: Oguz Altun, Vijaya B. Rentala, Gabriel J. Gomez, Baher S. Haroun