Patents by Inventor Baher S. Haroun

Baher S. Haroun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Digital time-interleaved RF-PWM transmitter
    Patent number: 8831085
    Abstract: A method for transmitting radio frequency (RF) signals is provided. In-phase (I) and quadrature (Q) signals are received and filtered using sigma-delta modulation. I and Q pulse width modulation signals are generated from the filtered I and Q signals and interleaved so as to generate a time-interleaved signal. The time-interleaved signal is then amplified to generate the RF signals.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Rahmi Hezar, Lei Ding, Joonhoi Hur, Baher S. Haroun
  • 1149.1 TAP LINKING MODULES
    Publication number: 20140215282
    Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.
    Type: Application
    Filed: March 31, 2014
    Publication date: July 31, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Lee D. Whetsel, Baher S. Haroun, Brian J. Lasher, Anjali Vij
  • Delay locked loop
    Patent number: 8786338
    Abstract: A method for providing a plurality of narrow pulses is provided. A first pulse having a first width is received by a delay line having a plurality of delay cells. This first pulse has a first width. In response to this first pulse, a plurality of second pulses is generated by the delay line, where each second pulse has a second width that is less than the first width. First and second delay pulses are also generated by the delay line, and a delay for each delay cell in the delay line can then be adjusted if a rising edge of the second delay pulse is misaligned with a falling edge of the first delay pulse.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: July 22, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Vijay B. Rentala, Srinath M. Ramaswamy, Brian P. Ginsburg, Eunyoung Seok, Baher S. Haroun
  • TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS
    Publication number: 20140181608
    Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
    Type: Application
    Filed: February 26, 2014
    Publication date: June 26, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Baher S. Haroun, Lee D. Whetsel
  • LINC transmitter with improved efficiency
    Patent number: 8744378
    Abstract: A radio frequency (RF) transmitter is provided. The RF transmitter includes first and second drivers that are configured to receive first and second sets of complementary RF signals. Restoration circuits are coupled to the first and second drivers, and a bridge circuit is coupled to the first and second restoration circuits. By having the restoration circuits and the bridge circuit, a common mode impedance and a differential impedance can be provided, where the common mode impedance is lower than the differential impedance.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: June 3, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Joonhoi Hur, Rahmi Hezar, Lei Ding, Baher S. Haroun
  • Shifting instruction data through IRS of IC TAP and TLM
    Patent number: 8726111
    Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: May 13, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Lee D. Whetsel, Baher S. Haroun, Brian J. Lasher, Anjali Vij
  • Tap and linking module TDO register, gating for TCK and TMS
    Patent number: 8713389
    Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: April 29, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Baher S. Haroun, Lee D. Whetsel
  • FINE GRAINED DUTY CYCLING AND TIMING CONTROL FOR PULSED RADAR
    Publication number: 20140111366
    Abstract: A method is provided. A first edge on a first gating signal is generated, and a local oscillator and a shared clocking circuit with the first edge on the first gating signal. A second edge on a second gating signal is generated following the first edge on the first gating signal, and a receiver circuit is activated with the second edge on the second gating signal, where the receiver circuit includes a mixer. A transmit pulse following the first edge on the first gating signal is generated with the transmit pulse having a third edge. A switch that short circuits outputs of the mixer is then released following the later of the third edge of the transmit pulse and a delay.
    Type: Application
    Filed: October 23, 2012
    Publication date: April 24, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Brian P. Ginsburg, Srinath M. Ramaswamy, Vijay B. Rentala, Eunyoung Seok, Baher S. Haroun
  • Systems and Methods of Tone Management in Hysteretic Mode DC to DC Converter
    Publication number: 20140097810
    Abstract: As disclosed herein, two hysteresis levels, a high level a low level, may be used to set a period (and the switching frequency) of the output voltage of a DC-DC converter, as well as the output ripple of the converter. These two thresholds may be changed using a set of switches. By controlling the sequence and the duration of the on-time of the switches, spectral spurs in the output can be controlled and the amplitude and the frequency band of interest can be reduced. Additional spur reduction may be possible by randomizing the control of the switches.
    Type: Application
    Filed: October 8, 2012
    Publication date: April 10, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Harikrishna Parthasarathy, Srinivas Venkata Veeramreddi, Sudhir Polarouthu, Baher S. Haroun
  • Transformer power combiner with filter response
    Patent number: 8654867
    Abstract: A method for generating an amplified radio frequency (RF) signal is provided. In-phase (I) and quadrature (Q) signals are received and interleaved so as to generate a time-interleaved signal. Delayed time-interleaved signals are then generated from the time interleaved signal, and each of the delayed time-interleaved signals is amplified so as to generate a plurality of amplified signals. The amplified signals are then combined with a transformer, where the delayed time-interleaved signals are arranged to generate a filter response with the transformer.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: February 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Rahmi Hezar, Lei Ding, Joonhoi Hur, Baher S. Haroun
  • TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS
    Publication number: 20140040689
    Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
    Type: Application
    Filed: October 2, 2013
    Publication date: February 6, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Baher S. Haroun, Lee D. Whetsel
  • 1149.1 TAP LINKING MODULES
    Publication number: 20130305108
    Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.
    Type: Application
    Filed: July 10, 2013
    Publication date: November 14, 2013
    Inventors: Lee D. Whetsel, Baher S. Haroun, Brian J. Lasher, Anjali Vij
  • One agumentation instruction register coupled to plural TAP instruction registers
    Patent number: 8578225
    Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: November 5, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Baher S. Haroun, Lee D. Whetsel
  • INTERCHIP COMMUNICATION USING AN EMBEDDED DIELECTRIC WAVEGUIDE
    Publication number: 20130265733
    Abstract: An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 10, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Juan A. Herbsommer, Robert F. Payne, Marco Corsi, Baher S. Haroun, Hassan Ali
  • INTERCHIP COMMUNICATION USING EMBEDDED DIELECTRIC AND METAL WAVEGUIDES
    Publication number: 20130265734
    Abstract: An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 10, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Juan A. Herbsommer, Robert F. Payne, Marco Corsi, Baher S. Haroun, Hassan Ali
  • INTERCHIP COMMUNICATION USING A DIELECTRIC WAVEGUIDE
    Publication number: 20130265732
    Abstract: An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 10, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Juan A. Herbsommer, Robert F. Payne, Marco Corsi, Baher S. Haroun, Hassan Ali
  • Wireless Chip-to-Chip Switching
    Publication number: 20130258892
    Abstract: Embodiments of the invention provide a system and method for chip to chip communications in electronic circuits. A router or switch receives data packets at input port ASICs. A routing table on the input port ASIC or on a routing ASIC is used to identify a destination port ASIC based upon header information in the data packet. The data packet is transmitted from the input port ASIC to the destination port ASIC using millimeter wave signals that are transmitted across a waveguide or a wireless interface.
    Type: Application
    Filed: May 24, 2013
    Publication date: October 3, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Nirmal Chindhu Warke, Srinath Hosur, Martin J. Izzard, Siraj Akhtar, Baher S. Haroun, Marco Corsi
  • TSV Testing Using Test Circuits and Grounding Means
    Publication number: 20130249590
    Abstract: This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 26, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lee D. Whetsel, Baher S. Haroun
  • PULSE WIDTH MODULATION SCHEME WITH REDUCED HARMONICS AND SIGNAL IMAGES
    Publication number: 20130241663
    Abstract: A method is provided. An input signal is received, and a noise-shaped signal is generated from the input signal. The noise-shaped signal is formed from a plurality of noise-shaping levels. A pulse stream is generated from the noise-shaped signal over a plurality of periods, where each period has a plurality of frames. The pulse stream also includes a plurality of pulse sets, where each pulse set is associated with at least one of the noise-shaping levels, and, for each pulse set having a total pulse width for its period that is less than its period and greater than zero, each pulse set includes at least one pulse in each frame for its period.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 19, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Lei Ding, Rahmi Hezar, Joonhoi Hur, Baher S. Haroun
  • FREE-FLY CLASS D POWER AMPLIFIER
    Publication number: 20130234795
    Abstract: A method is provided. A first enable signal is asserted so as to enable a first driver, where the first driver has a first output and a first parasitic capacitance. A second enable signal is asserted so as to enable a second driver, where the second driver has a second output and a second parasitic capacitance. The first and second outputs are coupled together by a switching network when the second driver is enabled. Pulses from complementary first and second radio frequency (RF) signals are applied to the first driver, where there is a first set of free-fly intervals between consecutive pulses from the first and second RF signals, and pulses from complementary third and fourth RF signals are applied to the second driver, wherein there is a second set of free-fly interval between consecutive pulses from the third and fourth RF signals.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 12, 2013
    Applicant: Texas Instruments Incorporation
    Inventors: Joonhoi Hur, Lei Ding, Rahmi Hezar, Baher S. Haroun