Patents by Inventor Baher S. Haroun

Baher S. Haroun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RELAXATION OSCILLATOR WITH CURRENT AND VOLTAGE OFFSET CANCELLATION
    Publication number: 20160013753
    Abstract: A relaxation oscillator reduces temperature sensitivity and phase noise at low offset frequency by periodically swapping a first current and a second current so that after the first current has been input to a first pair of circuits and the second current has been input to a second pair of circuits, the second current is input to the first pair of circuits and the first current is input to the second pair of circuits.
    Type: Application
    Filed: July 12, 2014
    Publication date: January 14, 2016
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kai Yiu Tam, Ali Kiaei, Baher S. Haroun
  • CHIP TO DIELECTRIC WAVEGUIDE INTERFACE FOR SUB-MILLIMETER WAVE COMMUNICATIONS LINK
    Publication number: 20150280320
    Abstract: In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.
    Type: Application
    Filed: June 9, 2015
    Publication date: October 1, 2015
    Inventors: Baher S. Haroun, Marco Corsi, Siraj Akhtar, Nirmal C. Warke
  • 1149.1TAP LINKING MODULES
    Publication number: 20150260791
    Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.
    Type: Application
    Filed: June 2, 2015
    Publication date: September 17, 2015
    Inventors: Lee D. Whetsel, Baher S. Haroun, Brian J. Lasher, Anjali Vij
  • TDO multiplexers series coupling augmentation instruction register with instruction registers
    Patent number: 9134376
    Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: September 15, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Baher S. Haroun, Lee D. Whetsel
  • Negative audio signal voltage protection circuit and method for audio ground circuits
    Patent number: 9136796
    Abstract: Self-grounded circuitry (10) includes a signal channel conducting an output voltage (VOUT1). A charge pump (2) powered by a reference voltage (VDD) produces a control voltage (VCP). The control signal is at a low level if the reference voltage is low and is boosted to a high level if the reference voltage is high. A ground switch circuit (15) includes a depletion mode transistor (MP1) having a source coupled to the output voltage, a gate coupled to the control voltage, and a drain coupled to ground. The transistor includes a well region (4-1) and a parasitic substrate diode (D3-1).
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: September 15, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: David H. Elwart, II, Vikas Suma Vinay, Christopher M. Graves, Baher S. Haroun
  • Calibration scheme for gas absorption spectra detection
    Patent number: 9128023
    Abstract: A technique for removing the background from a transmission spectrum including determining performance characteristics of a detector, measuring a transmission spectrum that includes an absorption line, determining performance characteristics of a gas cell, and removing a background spectrum from the transmission spectrum by combining the transmission spectrum with the performance characteristics of the detector and the performance characteristics of the gas cell.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: September 8, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Phillip Michel Nadeau, Baher S. Haroun, Srinath M. Ramaswamy
  • Chip to dielectric waveguide interface for sub-millimeter wave communications link
    Patent number: 9123737
    Abstract: In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: September 1, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Baher S. Haroun, Marco Corsi, Siraj Akhtar, Nirmal C. Warke
  • Linking module with IC and core TAP output enable leads
    Patent number: 9075113
    Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: July 7, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lee D. Whetsel, Baher S. Haroun, Brian J. Lasher, Anjali Vij
  • High speed digital interconnect and method
    Patent number: 9070703
    Abstract: In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: June 30, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Baher S. Haroun, Marco Corsi, Siraj Akhtar, Nirmal C. Warke
  • Switch pairs between resistor network and high/low DC converter comparator input
    Patent number: 9048728
    Abstract: Two hysteresis levels, a high level and a low level, may be used to set a period (and the switching frequency) of the output voltage of a DC-DC converter, as well as the output ripple of the converter. These two thresholds may be changed using pairs of switches. By controlling the sequence and the duration of the on-time of the switches, spectral spurs in the output can be controlled and the amplitude and the frequency band of interest can be reduced. Additional spur reduction may be possible by randomizing the control of the switches.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: June 2, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Harikrishna Parthasarathy, Srinivas Venkata Veeramreddi, Sudhir Polarouthu, Baher S. Haroun
  • TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS
    Publication number: 20150135029
    Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
    Type: Application
    Filed: January 26, 2015
    Publication date: May 14, 2015
    Inventors: Baher S. Haroun, Lee D. Whetsel
  • Fine grained duty cycling and timing control for pulsed radar
    Patent number: 8994585
    Abstract: A method is provided. A first edge on a first gating signal is generated, and a local oscillator and a shared clocking circuit with the first edge on the first gating signal. A second edge on a second gating signal is generated following the first edge on the first gating signal, and a receiver circuit is activated with the second edge on the second gating signal, where the receiver circuit includes a mixer. A transmit pulse following the first edge on the first gating signal is generated with the transmit pulse having a third edge. A switch that short circuits outputs of the mixer is then released following the later of the third edge of the transmit pulse and a delay.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: March 31, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Brian P. Ginsburg, Srinath M. Ramaswamy, Vijay B. Rentala, Eunyoung Seok, Baher S. Haroun
  • IC with connections between linking module and test access ports
    Patent number: 8977918
    Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: March 10, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Baher S. Haroun, Lee D. Whetsel
  • Pipelined continuous-time sigma delta modulator
    Patent number: 8970411
    Abstract: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: March 3, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Baher S. Haroun, Venkatesh Srinivasan, Patrick Satarzadeh, Marco Corsi
  • Negative Audio Signal Voltage Protection Circuit and Method for Audio Ground Circuits
    Publication number: 20140369520
    Abstract: Self-grounded circuitry (10) includes a signal channel conducting an output voltage (VOUT1). A charge pump (2) powered by a reference voltage (VDD) produces a control voltage (VCP). The control signal is at a low level if the reference voltage is low and is boosted to a high level if the reference voltage is high. A ground switch circuit (15) includes a depletion mode transistor (MP1) having a source coupled to the output voltage, a gate coupled to the control voltage, and a drain coupled to ground. The transistor includes a well region (4-1) and a parasitic substrate diode (D3-1).
    Type: Application
    Filed: June 18, 2013
    Publication date: December 18, 2014
    Inventors: David H. Elwart, II, Vikas Suma Vinay, Christopher M. Graves, Baher S. Haroun
  • DETECTION AND LOCKING TO THE ABSORPTION SPECTRA OF GASSES IN THE MILLIMETER-WAVE REGION
    Publication number: 20140368377
    Abstract: A frequency reference device that includes a frequency reference generation unit to generate a frequency reference signal based on an absorption line of a gas.
    Type: Application
    Filed: June 12, 2013
    Publication date: December 18, 2014
    Inventors: Phillip Michel NADEAU, Django TROMBLEY, Baher S. HAROUN, Srinath Mathur RAMASWAMY
  • CALIBRATION SCHEME FOR GAS ABSORPTION SPECTRA DETECTION
    Publication number: 20140368376
    Abstract: A technique for removing the background from a transmission spectrum including determining performance characteristics of a detector, measuring a transmission spectrum that includes an absorption line, determining performance characteristics of a gas cell, and removing a background spectrum from the transmission spectrum by combining the transmission spectrum with the performance characteristics of the detector and the performance characteristics of the gas cell.
    Type: Application
    Filed: June 12, 2013
    Publication date: December 18, 2014
    Inventors: Phillip Michel NADEAU, Baher S. HAROUN, Srinath M. RAMASWAMY
  • TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS
    Publication number: 20140359387
    Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
    Type: Application
    Filed: August 15, 2014
    Publication date: December 4, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Baher S. Haroun, Lee D. Whetsel
  • CAPACITIVE SENSOR
    Publication number: 20140292354
    Abstract: A capacitive sensor has at least first and second conductive areas so that a first capacitance is formed between the first conductive area and a surface, and a second capacitance is formed between the second conductive area and the surface, and the ratio of the first capacitance to the second capacitance has a predetermined value only when the sensor is at a predetermined distance from the surface.
    Type: Application
    Filed: March 27, 2013
    Publication date: October 2, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Baher S. Haroun, Rajarshi Mukhopadhyay, Paul Merle Emerson
  • IC test linking module with augmentation instruction shift register
    Patent number: 8850279
    Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: September 30, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Baher S. Haroun, Lee D. Whetsel