Abstract: A radio frequency (RF) transmitter includes transceiver circuitry coupled to front end circuitry via an interconnect signal path. The transceiver circuitry is configured to generate a number of frequency-shifted RF beamforming signals such that each one of the frequency-shifted RF beamforming signals has a different frequency, and multiplex the frequency-shifted RF beamforming signals to provide a multiplexed interconnect signal. The front-end circuitry is configured to receive the multiplexed interconnect signal from the transceiver circuitry via the interconnect signal path, demultiplex the multiplexed interconnect signal to isolate each of the frequency-shifted RF beamforming signals, shift a frequency of each one of the frequency-shifted RF beamforming signals to provide a number of RF beamforming signals, and transmit each of the RF beamforming signals from a different antenna.

Abstract: A power amplifier system having a power amplifier with a signal input and a signal output, bias circuitry coupled to the signal input, and a radio frequency (RF) peak detector having an input coupled to the signal output is disclosed. The RF peak detector is configured to generate a peak voltage signal. Temperature-compensated overvoltage protection circuitry coupled between an output of the RF peak detector and a control input of the bias circuitry is configured to respond to the peak voltage signal crossing over a predetermined peak voltage threshold and to provide an overvoltage protection control signal to cause the bias circuitry to adjust biasing for the power amplifier to reduce an overvoltage condition at the RF peak detector input.

Abstract: The present disclosure relates to a bulk complementary-metal-oxide-semiconductor (CMOS) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the thinned device die. Herein, a silicon material with a resistivity between 5 Ohm-cm and 30000 Ohm-cm does not exist between the second mold compound and the thinned device die.

Abstract: RF switching circuitry includes a plurality of FETs coupled between an input node, an output node, and a gate drive node. When a positive power supply voltage is provided at the gate drive node, the plurality of FETs turn on and provide a low impedance path between the input node and the output node. When a negative power supply voltage is provided at the gate drive node, the plurality of FETs turn off and provide a high impedance path between the input node and the output node. Switch acceleration circuitry in the RF switching circuitry includes a bypass FET and multi-level driver circuitry. The bypass FET selectively bypasses the common resistor in response to a multi-level drive signal. The multi-level driver circuitry uses a built-in gate to capacitance of the bypass FET to provide the multi-level drive signal at an overvoltage that is above the positive power supply voltage.

Abstract: The present disclosure relates to a semiconductor package with reduced parasitic coupling effects, and a process for making the same. The disclosed semiconductor package includes a thinned flip-chip die and a first mold compound component with a dielectric constant no more than 7. The thinned flip-chip die includes a back-end-of-line (BEOL) layer with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, a device layer over the upper surface of the BEOL layer, and a buried oxide (BOX) layer over the device layer. The BEOL layer includes a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion. Herein, the first mold compound component extends through the BOX layer and the device layer to the first surface portion.

Abstract: Embodiments of radio frequency (RF) filtering circuitry are disclosed. In one embodiment, the RF filtering circuitry includes a first port, a second port, a first RF filter path, and a second RF filter path. The first RF filter path is connected between the first port and the second port and includes at least a pair of weakly coupled resonators. The weakly coupled resonators are configured such that a first transfer response between the first port and the second port defines a first passband. The second RF filter path is coupled to the first RF filter path and is configured such that the first transfer response between the first port and the second port defines a stopband adjacent to the first passband without substantially increasing ripple variation of the first passband defined by the first transfer response.

Abstract: A radio frequency switch having an N number of switch cells coupled in series is disclosed. Each of the switch cells includes a field-effect transistor (FET), wherein a source of switch cell 1 is coupled to a first port, a drain of switch cell N is coupled to a second port, and a drain of switch cell X is coupled to a source of switch cell X+1 for switch cell 1 through switch cell N. A first diode stack has a first anode coupled to the body of switch cell X and a first cathode coupled to a drain of switch cell X+1 for switch cell 1 through switch cell N?1, and a second diode stack has a second anode coupled to the body of switch cell X and a second cathode coupled to the source of switch cell X?1 for switch cell 2 through switch cell N.

Abstract: A power amplifier system having a power amplifier with a signal input and a signal output and bias circuitry is disclosed. The bias circuitry includes a bandgap reference circuit coupled between a reference node and a fixed voltage node. A bias generator has a bias input coupled to the reference node and a bias output coupled to the signal input. Also included is a first digital-to-analog converter having a first converter output coupled to the reference node, a first voltage input, and a first digital input, wherein the first digital-to-analog converter is configured to adjust a reference voltage at the reference node in response to a first digital setting received at the first digital input. The first digital setting correlates with an indication of temperature of the power amplifier.

Abstract: A power amplifier system is disclosed that includes a power amplifier having a first signal input, a first signal output, second signal input, and a second signal output. The power amplifier system further includes cross-coupled bias circuitry having a first transistor with a first collector coupled to the first signal input, a first base coupled to the second signal input, and a first emitter coupled to a fixed voltage node, a second transistor with a second collector coupled to the second signal input, a second base coupled to the first signal input, and a second emitter coupled to the fixed voltage node.

Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.

Abstract: Embodiments of electronic devices, such as integrated circuit (IC) packages are disclosed. In one embodiment, an electronic device includes a first substrate and a second substrate. The first substrate has a first substrate body and a first inductor portion integrated into the first substrate body. Additionally, the second substrate comprises a second substrate body and a second inductor portion integrated into the second substrate body. The second substrate is mounted on the first substrate such that such that the second inductor portion is positioned over the first inductor portion and such that the second inductor portion is electrically connected to the first inductor portion so that the first inductor portion and the second inductor portion form a three dimensional (3D) inductor. By using two substrates, the 3D inductor can be increased in height while still allowing the substrates to be miniaturized and standardized for an IC package.

Abstract: The present disclosure relates to an air-cavity module having a thinned semiconductor die and a mold compound. The thinned semiconductor die includes a back-end-of-line (BEOL) layer, an epitaxial layer over the BEOL layer, and a buried oxide (BOX) layer with discrete holes over the epitaxial layer. The epitaxial layer includes an air-cavity, a first device section, and a second device section. Herein, the air-cavity is in between the first device section and the second device section and directly in connection with each discrete hole in the BOX layer. The mold compound resides directly over at least a portion of the BOX layer, within which the discrete holes are located. The mold compound does not enter into the air-cavity through the discrete holes.

Abstract: An apparatus with a body layer disposed over a substrate is disclosed. The body layer has first and second diffusion areas with a first current collection area between the two. A plurality of first drain/source (D/S) diffusions spaced parallel with one another resides within the first diffusion area. A plurality of first channel regions resides within the first diffusion area such that each of the plurality of first channel regions resides between an adjacent pair of the plurality of the first D/S diffusions. A plurality of second D/S diffusions resides within the second diffusion area and are spaced parallel with one another. A plurality of second channel regions reside within the second diffusion area such that each of the plurality of second channel regions resides between an adjacent pair of the plurality of the second D/S diffusions. A first current collection diffusion resides within the first current collection area.

Abstract: A power amplifier system having a power amplifier with a signal input and a signal output, bias circuitry coupled to the signal input, and a radio frequency (RF) peak detector having an input coupled to the signal output is disclosed. The RF peak detector is configured to generate a peak voltage signal. Temperature-compensated overvoltage protection circuitry coupled between an output of the RF peak detector and a control input of the bias circuitry is configured to respond to the peak voltage signal crossing over a predetermined peak voltage threshold and to provide an overvoltage protection control signal to cause the bias circuitry to adjust biasing for the power amplifier to reduce an overvoltage condition at the RF peak detector input.

Abstract: A power amplifier system is disclosed that includes a power amplifier having a first signal input, a first signal output, second signal input, and a second signal output. The power amplifier system further includes cross-coupled bias circuitry having a first transistor with a first collector coupled to the first signal input, a first base coupled to the second signal input, and a first emitter coupled to a fixed voltage node, a second transistor with a second collector coupled to the second signal input, a second base coupled to the first signal input, and a second emitter coupled to the fixed voltage node.

Abstract: A broadband power amplifier circuit is provided. The broadband power amplifier circuit includes an amplifier circuit configured to amplify a radio frequency (RF) signal to an output power based on a bias voltage and a supply voltage. Given that the output power of the RF signal may rise and fall from time to time, the broadband power amplifier circuit is configured to opportunistically increase or decrease the bias voltage in a defined future time (e.g., a future time slot or a future symbol duration) based on the output power in the defined future time. When necessary, the broadband power amplifier may be further configured to adjust the supply voltage and/or attenuate the RF signal based on the output power. As such, it may be possible to maintain class-A operation mode for the amplifier circuit. As a result, the amplifier circuit may maintain linearity and avoid memory effect with improved efficiency.

Abstract: A stacked field-effect transistor (FET) switch is disclosed. The stacked FET switch has a first FET device stack that is operable in an on-state and in an off-state and is made up of a first plurality of FET devices coupled in series between a first port and a second port, wherein the first FET device stack has a conductance that decreases with increasing voltage between the first port and the second port. The stacked FET switch also includes a second FET device stack that is operable in the on-state and in the off-state and is made up of a second plurality of FET devices coupled in series between the first port and the second port, wherein the second FET device stack has a conductance that increases with increasing voltage between the first port and the second port.

Abstract: A power amplifier system is disclosed that includes a power amplifier having a first signal input, a first signal output, second signal input, and a second signal output. The power amplifier system further includes cross-coupled bias circuitry having a first transistor with a first collector coupled to the first signal input, a first base coupled to the second signal input, and a first emitter coupled to a fixed voltage node, a second transistor with a second collector coupled to the second signal input, a second base coupled to the first signal input, and a second emitter coupled to the fixed voltage node.

Abstract: A radio frequency switch having an N number of switch cells coupled in series is disclosed. Each of the switch cells includes a field-effect transistor (FET), wherein a source of switch cell 1 is coupled to a first port, a drain of switch cell N is coupled to a second port, and a drain of switch cell X is coupled to a source of switch cell X+1 for switch cell 1 through switch cell N. A first diode stack has a first anode coupled to the body of switch cell X and a first cathode coupled to a drain of switch cell X+1 for switch cell 1 through switch cell N?1, and a second diode stack has a second anode coupled to the body of switch cell X and a second cathode coupled to the source of switch cell X?1 for switch cell 2 through switch cell N.

Abstract: The present disclosure relates to a semiconductor package with reduced parasitic coupling effects, and a process for making the same. The disclosed semiconductor package includes a thinned flip-chip die and a first mold compound component with a dielectric constant no more than 7. The thinned flip-chip die includes a back-end-of-line (BEOL) layer with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, a device layer over the upper surface of the BEOL layer, and a buried oxide (BOX) layer over the device layer. The BEOL layer includes a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion. Herein, the first mold compound component extends through the BOX layer and the device layer to the first surface portion.