Abstract: Three-dimensional (3D) memory structures and methods of formation of same are provided herein. In some embodiments, a 3D memory fabrication structure includes: a base silicon (Si) layer; a silicon germanium (SiGe) layer disposed above the base Si layer; and a doped silicon (Si) layer disposed on at least one side of the SiGe layer, wherein the doped Si layer contains a dopant that is at least one of carbon (C) or boron (B).

Abstract: Exemplary methods of semiconductor processing may include providing an etchant precursor to a processing region of a semiconductor processing chamber. A structure may be disposed within the processing region. The structure may include a first silicon-containing material. The structure may include a second silicon-containing material, an oxygen-containing material, or both. The methods may include contacting the structure with the etchant precursor. The contacting with the etchant precursor may etch at least a portion of the second silicon-containing material or the oxygen-containing material from the structure. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting the structure with the carbon-containing precursor. The contacting with the carbon-containing precursor may replenish carbon in the first silicon-containing material.

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices, fin field effect transistors (FinFETs) in particular, and methods of manufacturing such devices having improved effective capacitance (Ceff). The FinFETs include a gate structure in which airgaps are provided by recessing a high-k material layer disposed between the gate structure and a spacer layer, thereby reducing the effective dielectric constant in the high-k dielectric layer and improving effective capacitance (Ceff) of the device.

Abstract: The present technology includes vertical cell array transistor (VCAT) with improved gate induced leakage current. The arrays one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The arrays include one or more channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit lines intersect with a source/drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where at least one word includes a first section adjacent to the source/drain region and a second section adjacent to the gate region, where the second section contains a high work function material and the first section contains a low work function material.

Abstract: Vertical cell dynamic random-access memory (DRAM) arrays and methods of forming arrays with improved stability and word line resistivity are provided. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels. In addition, arrays include a bridge extending between a first channel of the plurality of channels and a second channel of the plurality of channels, where the first channel is spaced apart from the second channel in a row extending in the second horizontal direction. Arrays include a gate formed around at least a portion of the plurality of channels and the bridge.

Abstract: A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.

Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.

Abstract: A semiconductor device and a method for manufacturing thereof. A substrate is provided. One or more groups of layers are formed on top of the substrate. A compensation layer is formed on top of at least one group of layers. At least one silicon layer is formed on top of the compensation layer. At least a portion of one or more layers in the one or more groups of layers is etched. The semiconductor device is formed.

Abstract: A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) includes forming placeholders, each interfacing with an extension region via a cap layer, in recesses formed in portions of a substrate isolated by shallow trench isolations (STIs), the recesses extending into an inter-layer dielectric (ILD) formed on the substrate, removing the placeholders selectively to the substrate, the cap layers, and the STIs, forming selective cap layers at bottoms of the recesses, performing a substrate removal process to isotropically etch the substrate within the recesses, performing a conformal deposition process to form a spacer on exposed surfaces of the substrate and the selective cap layers within the recesses, sculpting the spacer on sidewalls of the substrate and the STIs within the recesses, performing a cap layer removal process to remove the cap layers within the recesses, and forming metal contacts within the recesses.

Abstract: Methods of manufacturing memory devices are provided. The method comprises forming a first epitaxial layer on a substrate; and forming a memory array on the first epitaxial layer, the memory array comprising a memory stack of alternating layers of an oxide material and a metal material on the first epitaxial layer, at least one memory cell extending from the first epitaxial layer through the memory stack, and a slit filled with a fill material adjacent to the at least one memory cell.

Abstract: A cluster tool for forming an interconnection structure includes a pre-clean chamber, a selective chemical vapor deposition (CVD) chamber, a plasma-enhanced CVD (PECVD) chamber, one or more transfer chambers coupled to the pre-clean chamber, the selective CVD chamber, and the PECVD chamber, and configured to transfer the interconnection structure between the pre-clean chamber, the selective CVD chamber, and the PECVD chamber without breaking vacuum environment, and a controller configured to cause pre-cleaning of an exposed surface of a metal layer formed within a first dielectric layer of the interconnection structure in the pre-clean chamber, selective deposition of a cap layer on the pre-cleaned surface of the metal layer in the selective CVD chamber, and deposition of deposit a second dielectric layer on the cap layer and an exposed surface of the first dielectric layer in the PECVD chamber.

Abstract: A semiconductor device and a method for manufacturing thereof. A substrate is provided. At least one silicon layer is formed on top of the substrate. At least one silicon-germanium layer is formed on top of at least one silicon layer. At least one silicon-germanium layer includes at least one n-type dopant. The semiconductor device having at least one silicon layer and at least one silicon-germanium layer is formed.

Abstract: A semiconductor device including a substrate; a continuous buried oxide layer (BOX) formed on the substrate; and a plurality of nanosheet gate-all-round (GAA) device structures on the BOX, wherein a first plurality of stacked gates of the nanosheet GAA device structures are disposed in a logic portion of the substrate and have a first nanosheet width, wherein a second plurality of stacked gates of the nanosheet GAA device structures are disposed in a high density region of the substrate and have a second nanosheet width less than the first nanosheet width, wherein the nanosheet GAA device structures are disposed directly on the continuous buried oxide layer, and wherein a bottom layer of the nanosheet GAA device structures is a bottom gate formed directly on the BOX.

Abstract: Methods and structures to achieve low voltage (LV) and high voltage (HV) scale-down by suppressing the short channel effect of LV as well as increasing breakdown voltage of HV transistor are provided. A semiconductor device comprises a first transistor comprising a first well region of a first conductivity type, a first gate region disposed above the first well region, and a first contact region including a first epitaxial semiconductor adjacent to the first gate region; and a second transistor comprising a second well region of a second conductivity, a second gate region disposed above the second well region, and a second contact region including a second epitaxial semiconductor adjacent to the second gate region.

Abstract: In some embodiments, a method for forming a multiple die stack comprises forming a first circuit wafer with multiple first circuit dies and a first circuit support layer on a bottom of the first circuit wafer where each first circuit die has a power and circuit layer underlying a power and signal layer, forming an interposer wafer with multiple interposer dies and an interposer support layer on a top of the interposer wafer where each interposer die has a power and signal layer underlying a power via and signal via layer, and hybrid bonding a top surface of the first circuit wafer to a bottom surface of the interposer wafer to form a first bonded wafer with electrical power and signal connections between the multiple first circuit dies and the multiple interposer dies where the interposer wafer provides structural support of the first bonded wafer during subsequent processing.

Abstract: A semiconductor device includes a dielectric isolation layer, a plurality of gates formed above the dielectric isolation layer, a plurality of source/drain regions above the dielectric isolation layer between the plurality of gates, and at least one contact placeholder for a backside contact. The at least one contact placeholder contacts a bottom surface of a first source/drain region of the plurality of source/drain regions. The semiconductor device further includes at least one backside contact contacting a bottom surface of a second source/drain region of the plurality of source/drain regions, and a buried power rail arranged beneath, and contacting the at least one backside contact.

Abstract: Exemplary semiconductor structures may include a substrate. The structures may include a first layer of silicon-and-oxygen-containing material overlying the substrate. The structures may include a second layer of silicon-and-oxygen-containing material. The structures may include a first layer of metal-and-oxygen-containing material between the first layer of silicon-and-oxygen-containing material and the second layer of silicon-and-oxygen-containing material. The first layer of metal-and-oxygen-containing material may include a first metal. The structures may include a second layer of metal-and-oxygen-containing material disposed within the first layer of metal-and-oxygen-containing material. The second layer of metal-and-oxygen-containing material may include a second metal. The structures may include a gate disposed within the second layer of metal-and-oxygen-containing material.

Abstract: A method for manufacturing a memory device includes depositing a seed layer in a memory hole extending through a memory stack. The seed layer includes particles, such as silicon particles. The seed layer is etched to produce etched particles. The etched particles act as nuclei for the growth of a crystalline channel material in the memory hole.

Abstract: A three-dimensional semiconductor (3D) device. The 3D device may include a substrate, and a monocrystalline layer stack. The monocrystalline layer stack may include at least one monocrystalline semiconductor layer, separated from, and disposed over a main surface of the substrate. The 3D device may further include a plurality of epitaxial heterostructures, integrally grown from the at least one monocrystalline semiconductor layer. As such, a first epitaxial heterostructure may be disposed on a lower surface of the at least one monocrystalline semiconductor layer, facing the substrate, and wherein a second epitaxial heterostructure may be disposed on an upper surface of the monocrystalline semiconductor layer, opposite the lower surface.

Abstract: A semiconductor structure includes a first active region and a second active region on a substrate, a metal plug electrically connected to the first active region via a contact layer and an interface layer, a bit line electrically connected to the second active region via a bit line contact plug, and a bit line spacer encapsulating the bit line, wherein the first active region and the second active region are lightly n-type doped, the substrate is p-type doped, and the contact layer is epitaxially grown and n-type doped with a graded doping profile that increases from an interface with the first active region to an interface with the interface layer.