Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor devices include a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break, and the second gate region includes a first gate enclosing the channel between the source region and the drain region. The self-aligned single diffusion break also contains a stressed dielectric material having a stress of about 500 MPa or greater.

Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break, and the second gate region includes a first gate enclosing the channel between the source region and the drain region. The self-aligned single diffusion break also contains a dielectric liner and a stressed metal fill, where the stressed metal fill exhibits a stress of about 350 MPa or greater.

Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain. Devices include a first gate region having a first self-aligned single diffusion break in a n-MOS region, and a second gate region includes having a self-aligned single diffusion break in a p-MOS region. The second self-aligned single diffusion break also contains a liner and a compressive stressed material, where the stressed metal fill exhibits a compressive stress of about 350 MPa or greater.

Abstract: A semiconductor structure includes a power distribution network including a first buried power rail, a power wire, and a first buried via electrically interconnecting the first buried power rail and the power wire. Each of the first buried power rail, the power wire, and the first buried via have a liner on a corresponding bottom surface thereof and sidewalls thereof. The structure also includes a dielectric layer outward of the power distribution network; a first field effect transistor outward of the dielectric layer; a first via trench contact electrically interconnecting a source/drain region of the transistor to the first buried power rail; a first outer wire outward of the first field effect transistor; and an electrical path electrically interconnecting the first outer wire with the power wire.

Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices, and inner spacer liners and inner spacers for GAA devices, are described. The methods comprise forming an inner spacer liner within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of recessed semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) alternatingly arranged in a plurality of stacked pairs. The inner spacer liner comprises a crystalline silicon-containing liner formed by a selective epitaxial growth (SEG) process. The crystalline silicon-containing liner may be doped with a dopant (e.g., a p-type dopant or an n-type dopant). One or more operations of the methods described herein are performed in situ in an integrated processing tool system.

Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices, and inner spacer liners and inner spacers for GAA devices, are described. The methods comprise performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and an inner spacer within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)). The amorphous silicon liner is conformally formed along the GAA device, including along the recessed semiconductor material layers and the corresponding plurality of channel layers, and the inner spacer is formed directly on the amorphous silicon liner. One or more operations of the methods described herein are performed in situ in an integrated processing tool system.

Abstract: A method of fabricating a semiconductor device comprises forming backside power rails in a dielectric layer arranged above a backside interlayer dielectric (BILD) layer or a semiconductor layer, forming a trench that extends through the BILD layer or the semiconductor layer and partly through the dielectric layer between the backside power rails, depositing a plurality of layers to form a backside metal-insulator-metal (MIM) capacitor in the trench, and forming a first contact to a first metal layer of the plurality of layers. Forming the first contact comprises forming first recesses in a second metal layer of the plurality of layers, and filling the first recesses with an insulative material. The method further comprises forming a second contact to the second metal layer. Forming the second contact comprises forming second recesses in the first metal layer, and filling the second recesses with the insulative material.

Abstract: A method of forming a multi-layer semiconductor device on a substrate includes forming a superlattice of a plurality of alternating first layers composed of a first material and second layers formed of a second material, removing the second layers of the superlattice, etching the first material layers to form trimmed first layers therefrom, wherein the quantity of material removed from different ones of the first layers are different amounts, forming a capping layer over the first layers, measuring at least one of the distance between the capping layers formed on the different ones of the first layers, the thicknesses of the different ones of the capping layers formed on different ones of the trimmed first layers, and the different thicknesses of the combined thickness of different ones of the trimmed first layers and the capping layer formed thereover, and based on differences in the measurements, calculating a new thickness of the etched first layers.

Abstract: Exemplary methods of semiconductor processing may include etching a portion of a silicon-containing material from a substrate disposed within a processing region of a semiconductor processing chamber. The silicon-containing material may extend into one or more recesses defined by alternating layers of material deposited on the substrate. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting a remaining silicon-containing material with the carbon-containing precursor. The contacting with the carbon-containing precursor may replenish carbon in the silicon-containing material. The methods may include providing a cleaning agent to the processing region of the semiconductor processing chamber. The methods may include contacting the substrate with the cleaning agent. The contacting with the cleaning precursor may remove surface oxide from the substrate.

Abstract: Embodiments of the present disclosure provide techniques for fabricating a semiconductor device with fewer via voids (e.g., gaps between a dielectric layer and a metal fill of the semiconductor device). One such technique involves forming a dielectric layer over a surface of a substrate, forming one or more openings in the dielectric layer, filling the one or more openings with a metal wherein the metal is disposed on a surface of each of the one or more openings, and implanting an oxygen containing species into the dielectric layer to provide a dose of the oxygen containing species to the surface of each of the one or more openings and the metal disposed thereon.

Abstract: Embodiments of the present disclosure are provide a method for fabricating a semiconductor device with fewer via voids (e.g., gaps between a dielectric layer and a metal fill of the semiconductor device). One such technique involves forming a dielectric layer, wherein at least a portion of the dielectric layer comprises a nonstoichiometric compound; forming one or more openings in the dielectric layer; filling the one or more openings with a metal, wherein the metal is disposed on a surface of each of the one or more openings; and exposing the dielectric layer and metal disposed in the openings to an oxidizing atmosphere, wherein exposing the dielectric layer and metal in the openings causes oxidation of the nonstoichiometric compound.

Abstract: A semiconductor structure including a first dielectric layer comprising a first conductive metal feature embedded in the first dielectric layer; and a second dielectric layer including a second conductive metal feature embedded in the second dielectric layer, the second conductive metal feature is above and directly contacts the first conductive metal feature, and an interface between the second conductive metal feature and the second dielectric layer includes a repeating scallop shape along its entire length.

Abstract: A method of forming a semiconductor memory device includes simultaneously filling a top portion of a first high aspect ratio (HAR) structure and a top portion a second HAR structure with a silicon-containing sacrificial layer by a cycle of a deposition process and an etch process, wherein the first HAR structure has a critical dimension (CD) of between 150 nm and 250 nm, and the second HAR structure has a CD of between 250 nm and 400 nm.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a first trench partially through a first substrate from a first side of the first substrate. The method also includes widening a bottom portion of the first trench to form a lateral footing area of the first trench. The method includes forming a first metallization in the first trench; forming a second trench through a second substrate from a second side of the second substrate to expose at least a portion of first metallization in an area corresponding to the lateral footing area of the first trench, the second side being opposite to the first side. The method also includes forming a second metallization in the second trench in contact with the first metallization.

Abstract: A semiconductor fabrication method that uses a graphene etch stop is disclosed. The method comprises forming a first set of trenches and a second set of trenches in a substrate. The first set of trenches are narrower than the second set of trenches. The method further comprises forming a graphene layer in the first and second sets of trenches. The method further comprises depositing a first conductor in the first and second sets of trenches. The method further comprises removing the first conductor from the second set of trenches using an etching process. The graphene layer acts as an etch stop for the etching process. The method further comprises depositing a second conductor in the second set of trenches. The second conductor is different than the first conductor.

Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.

Abstract: Semiconductor devices (e.g., GAA device structures) and processing methods and cluster tools for forming GAA device structures are described. The cluster tools for forming GAA device structures comprise a first etch chamber, a second etch chamber, and a third etch chamber. Each of the first etch chamber and the second etch chamber independently comprises a single-wafer chamber or an immersion chamber. One or more of the first etch chamber or the second etch chamber may be a wet etch chamber. In some embodiments, at least one of the first etch chamber, the second etch chamber, and the third etch chamber is a dry etch chamber. The cluster tool described herein advantageously reduces the number of cleaning processes, the total time between cleaning and processing operations, variations in time between processing and variation in sidewall loss compared to conventional cluster tools.

Abstract: A method of forming an electrical contact in a semiconductor structure includes performing a patterning process to form a hard mask on a semiconductor structure comprising a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region, wherein the hard mask covers an exposed surface of the first semiconductor region within the first opening, performing a first selective deposition process to form a contact layer on the exposed surface of the second semiconductor region within the second opening, and performing a second selective deposition process to form a cap layer on the contact layer.

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a semiconductor material between source regions and drain regions of the device. The method includes formation of a cladding material on a first material followed by a dry oxidation process resulting rearrangement of the cladding material and first material.

Abstract: A method of forming a contact layer in a semiconductor structure includes performing a pre-clean process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, wherein the exposed surfaces of the plurality of first and second semiconductor regions are each disposed within openings formed in a dielectric layer disposed over the substrate, performing a first selective epitaxial deposition process to form a first contact layer on the exposed surfaces of the first semiconductor regions and a second contact layer on the exposed surface of the second semiconductor regions, performing a patterning process to form a patterned stack, wherein the patterned stack comprises a patterned layer that comprises openings formed over the first contact layer disposed within each opening in the dielectric layer and a portion of the patterned layer that is disposed over each second contact layer disposed within each opening in the dielectric layer, a