Abstract: Embodiments of the invention include vertically stacked field-effect transistors (FETs). The vertically stacked FETs include at least one first transistor and at least one second transistor separated by a dielectric isolation layer. Gate material is adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material.

Abstract: A method of fabricating a semiconductor device comprises forming backside power rails in a dielectric layer arranged above a backside interlayer dielectric (BILD) layer or a semiconductor layer, forming a trench that extends through the BILD layer or the semiconductor layer and partly through the dielectric layer between the backside power rails, depositing a plurality of layers to form a backside metal-insulator-metal (MIM) capacitor in the trench, and forming a first contact to a first metal layer of the plurality of layers. Forming the first contact comprises forming first recesses in a second metal layer of the plurality of layers, and filling the first recesses with an insulative material. The method further comprises forming a second contact to the second metal layer. Forming the second contact comprises forming second recesses in the first metal layer, and filling the second recesses with the insulative material.

Abstract: A semiconductor structure includes a power distribution network including a first buried power rail, a power wire, and a first buried via electrically interconnecting the first buried power rail and the power wire. Each of the first buried power rail, the power wire, and the first buried via have a liner on a corresponding bottom surface thereof and sidewalls thereof. The structure also includes a dielectric layer outward of the power distribution network; a first field effect transistor outward of the dielectric layer; a first via trench contact electrically interconnecting a source/drain region of the transistor to the first buried power rail; a first outer wire outward of the first field effect transistor; and an electrical path electrically interconnecting the first outer wire with the power wire.

Abstract: A semiconductor device including a substrate; a continuous buried oxide layer (BOX) formed on the substrate; and a plurality of nanosheet gate-all-round (GAA) device structures on the BOX, wherein a first plurality of stacked gates of the nanosheet GAA device structures are disposed in a logic portion of the substrate and have a first nanosheet width, wherein a second plurality of stacked gates of the nanosheet GAA device structures are disposed in a high density region of the substrate and have a second nanosheet width less than the first nanosheet width, wherein the nanosheet GAA device structures are disposed directly on the continuous buried oxide layer, and wherein a bottom layer of the nanosheet GAA device structures is a bottom gate formed directly on the BOX.

Abstract: Embodiments of the invention include a multi-layer integrated circuit (IC) structure having a back-end-of-line (BEOL) region that includes a dielectric. A single damascene interconnect is in the BEOL region, wherein the single damascene interconnect includes a first line structure in a first line trench of the BEOL region; and a via structure in a via trench of the BEOL region. The first line structure includes a first line element and a first liner. The via structure includes a via element and a via liner. The first line element is physically coupled to inner walls of the first line trench through the first liner. The via element is physically coupled to inner walls of the via trench through the via liner. The first line element is physically coupled and electrically coupled to the via element at a first-line-via interface.

Abstract: A semiconductor fabrication method that uses a graphene etch stop is disclosed. The method comprises forming a first set of trenches and a second set of trenches in a substrate. The first set of trenches are narrower than the second set of trenches. The method further comprises forming a graphene layer in the first and second sets of trenches. The method further comprises depositing a first conductor in the first and second sets of trenches. The method further comprises removing the first conductor from the second set of trenches using an etching process. The graphene layer acts as an etch stop for the etching process. The method further comprises depositing a second conductor in the second set of trenches. The second conductor is different than the first conductor.

Abstract: A semiconductor device includes a dielectric isolation layer, a plurality of gates formed above the dielectric isolation layer, a plurality of source/drain regions above the dielectric isolation layer between the plurality of gates, and at least one contact placeholder for a backside contact. The at least one contact placeholder contacts a bottom surface of a first source/drain region of the plurality of source/drain regions. The semiconductor device further includes at least one backside contact contacting a bottom surface of a second source/drain region of the plurality of source/drain regions, and a buried power rail arranged beneath, and contacting the at least one backside contact.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a deep source/drain cavity and filling the cavity with a sacrificial material. The sacrificial material is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.

Abstract: Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. The wafer is then subjected to device and front-end processing. After front-end processing, the wafer undergoes hybrid bonding, and then the wafer is thinned. To thin the wafer, the silicon substrate layer, which has a starting first thickness, is ground to a second thickness, the second thickness less than the first thickness. After grinding, the silicon wafer is subjected to chemical mechanical planarization (CMP), followed by etching and CMP buffing, to reduce the thickness of the silicon to a third thickness, the third thickness less than the second thickness.

Abstract: Semiconductor devices and methods of manufacturing the same are described. Transistors are fabricated using a standard process flow. A via opening extending from the top surface of the substrate to a bottom surface of the wafer device is formed, thus allowing nano TSV for high density packaging, as well as connecting the device to the backside power rail. A metal is deposited in the via opening, and the bottom surface of the wafer device is bound to a bonding wafer. The substrate is optionally thinned, and a contact electrically connected to the metal is formed.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is crystallized. Epitaxially growth of the source and drain regions then proceeds, which growth advantageously occurring on the bottom and sidewalls of the source and drain regions.

Abstract: Exemplary integrated cluster tools may include a factory interface including a first transfer robot. The tools may include a wet clean system coupled with the factory interface at a first side of the wet clean system. The tools may include a load lock chamber coupled with the wet clean system at a second side of the wet clean system opposite the first side of the wet clean system. The tools may include a first transfer chamber coupled with the load lock chamber. The first transfer chamber may include a second transfer robot. The tools may include a second transfer chamber coupled with the first transfer chamber. The second transfer chamber may include a third transfer robot. The tools may include a metal deposition chamber coupled with the transfer chamber.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a first trench partially through a first substrate from a first side of the first substrate. The method also includes widening a bottom portion of the first trench to form a lateral footing area of the first trench. The method includes forming a first metallization in the first trench; forming a second trench through a second substrate from a second side of the second substrate to expose at least a portion of first metallization in an area corresponding to the lateral footing area of the first trench, the second side being opposite to the first side. The method also includes forming a second metallization in the second trench in contact with the first metallization.

Abstract: A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.

Abstract: A semiconductor structure including a first dielectric layer comprising a first conductive metal feature embedded in the first dielectric layer; and a second dielectric layer including a second conductive metal feature embedded in the second dielectric layer, the second conductive metal feature is above and directly contacts the first conductive metal feature, and an interface between the second conductive metal feature and the second dielectric layer includes a repeating scallop shape along its entire length.

Abstract: In a self-aligned fin cut process for fabricating integrated circuits, a sacrificial gate or an epitaxially-formed source/drain region is used as an etch mask in conjunction with a fin cut etch step to remove unwanted portions of the fins. The process eliminates use of a lithographically-defined etch mask to cut the fins, which enables precise and accurate alignment of the fin cut.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a first recess partially through a substrate from a first side of the substrate, forming a dielectric layer in the first recess, forming a second recess partially through the dielectric layer from the first side of the substrate, and forming a buried power rail (BPR) in the second recess of the dielectric layer. The method also includes thinning the substrate from a second side of the substrate to a level of the dielectric layer, the second side of the substrate being opposite to the first side of the substrate.

Abstract: The present invention provides fin cut techniques in a replacement gate process for finFET fabrication. In one aspect, a method of forming a finFET employs a dummy gate material to pin a lattice constant of patterned fins prior to a fin cut thereby preventing strain relaxation. A dielectric fill in a region of the fin cut (below the dummy gates) reduces an aspect ratio of dummy gates formed from the dummy gate material in the fin cut region, thereby preventing collapse of the dummy gates. FinFETs formed using the present process are also provided.

Abstract: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.

Abstract: A method is presented for reducing a reset current for a phase change memory (PCM). The method includes forming a bottom electrode, constructing a PCM cell structure including a plurality of phase change memory layers and a plurality of heat transfer layers, wherein the plurality of phase change memory layers are assembled in an alternating configuration with respect to the plurality of heat transfer layers, and forming a top electrode over the PCM cell structure. The plurality of phase change memory layers are arranged perpendicular to the top and bottom electrodes. Additionally, airgaps are defined adjacent the PCM cell structure.