Abstract: According to an embodiment of the present invention, self-aligned gate cap, comprises a gate located on a substrate; a gate cap surrounding a side of the gate; a contact region self-aligned to the gate; and a low dielectric constant oxide having a dielectric constant of less than 3.9 located on top of the gate. According to an embodiment of the present invention, a method of forming a self-aligned contact comprises removing at least a portion of an interlayer dielectric layer to expose a top surface of a gate cap located on a substrate; recessing the gate cap to form a recessed area; depositing a low dielectric constant oxide having a dielectric constant of less than 3.9 in the recessed area; and polishing a surface of the low dielectric constant oxide to expose a contact area.

Abstract: Compressive and tensile stress is induced, respectively, on semiconductor fins in the pFET and nFET regions of a monolithic semiconductor structure including FinFETs. A tensile stressor is formed from dielectric material and a second, compressive stressor is formed from metal. The stressors may be formed in fin cut regions of the monolithic semiconductor structure and are configured to provide stress in the direction of FinFET current flow. The dielectric material may be deposited on the monolithic semiconductor structure and later removed from the fin cut regions of the pFET region. Metal exhibiting compressive residual stress is then deposited in the fin cut regions from which the dielectric material was removed. Gate cut regions may also be filled with the dielectric stressor material to impart substantially uniaxial tensile stress perpendicular to the semiconductor fins and perpendicular to electrical current flow.

Abstract: A Phase-change-memory (PCM) cell and method of forming the PCM are provided. In an illustrative embodiment, a method of forming a PCM cell includes forming a first layer of a first germanium-antimony-tellurium (GST) type material over at least a portion of the bottom and sides of a pore through a dielectric layer of low dielectric material to a bottom electrode. The method also includes forming a second layer of a second GST type material over the first GST type material along the bottom and sides of the pore over the bottom electrode. The first GST type material is different from the second GST type material.

Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.

Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.

Abstract: A self-align metal contact for a phase control memory (PCM) element is provided that mitigates unwanted residual tantalum nitride (TaN) particles that would otherwise remain after patterning a TaN surface using an RIE process.

Abstract: Compressive and tensile stress is induced, respectively, on semiconductor fins in the pFET and nFET regions of a monolithic semiconductor structure including FinFETs. A tensile stressor is formed from dielectric material and a second, compressive stressor is formed from metal. The stressors may be formed in fin cut regions of the monolithic semiconductor structure and are configured to provide stress in the direction of FinFET current flow. The dielectric material may be deposited on the monolithic semiconductor structure and later removed from the fin cut regions of the pFET region. Metal exhibiting compressive residual stress is then deposited in the fin cut regions from which the dielectric material was removed. Gate cut regions may also be filled with the dielectric stressor material to impart substantially uniaxial tensile stress perpendicular to the semiconductor fins and perpendicular to electrical current flow.

Abstract: A source/drain contact includes a first portion arranged on a substrate and extending between a first gate and a second gate; a second portion arranged on the first portion and extending over the first gate and the second gate, the second portion including a partially recessed liner and a metal disposed on the partially recessed liner, and the partially recessed liner arranged on an endwall of the second portion and in contact with the first portion; and an oxide disposed around the second portion and on the first gate and the second gate.

Abstract: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.

Abstract: Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having self-aligned contacts. In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source/drain region of a substrate. A conductive gate is formed over a channel region of the semiconductor fin. A top source/drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source/drain region. A dielectric cap is formed over the top metallization layer.

Abstract: The present invention provides fin cut techniques in a replacement gate process for finFET fabrication. In one aspect, a method of forming a finFET employs a dummy gate material to pin a lattice constant of patterned fins prior to a fin cut thereby preventing strain relaxation. A dielectric fill in a region of the fin cut (below the dummy gates) reduces an aspect ratio of dummy gates formed from the dummy gate material in the fin cut region, thereby preventing collapse of the dummy gates. FinFETs formed using the present process are also provided.

Abstract: Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

Abstract: After forming a material stack including a gate dielectric, a work function metal and a cobalt gate electrode in a gate cavity formed by removing a sacrificial gate structure, the cobalt gate electrode is recessed by oxidizing the cobalt gate electrode to provide a cobalt oxide layer on a surface of the cobalt gate electrodes and removing the cobalt oxide layer from the surface of the cobalt gate electrodes by a chemical wet etch. The oxidation and oxide removal steps can be repeated until the cobalt gate electrode is recessed to any desired thickness. The work function metal can be recessed after the recessing of the cobalt gate electrode is completed or during the recessing of the cobalt gate electrode.

Abstract: A semiconductor device includes a first type nanosheet device having a first plurality of nanosheet portions alternately stacked with a first plurality of work function metal layers on a substrate, and a second type nanosheet device having a second plurality of nanosheet portions alternately stacked with a second plurality of work function metal layers on the substrate. The second type nanosheet device is spaced apart from the first type nanosheet device. The semiconductor device also includes a dielectric layer disposed in the space between the first and second type nanosheet devices. The first and second plurality of work function metal layers are directly disposed on the dielectric layer, and bottom surfaces of the directly disposed first and second plurality of work function metal layers are co-planar with each other.

Abstract: A semiconductor device includes a first type nanosheet device having a first plurality of nanosheet portions alternately stacked with a first plurality of work function metal layers on a substrate, and a second type nanosheet device having a second plurality of nanosheet portions alternately stacked with a second plurality of work function metal layers on the substrate. The second type nanosheet device is spaced apart from the first type nanosheet device. The semiconductor device also includes a dielectric layer disposed in the space between the first and second type nanosheet devices. The first and second plurality of work function metal layers are directly disposed on the dielectric layer, and bottom surfaces of the directly disposed first and second plurality of work function metal layers are co-planar with each other.

Abstract: Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

Abstract: A method for forming a device structure provides for forming a fin of a semiconductor material. A first contact is formed on the fin. A second contact is formed on the fin and spaced along a length of the fin from the first contact. A self-aligned gate electrode is formed on the fin that is positioned along the length of the fin between the first contact and the second contact.

Abstract: A method of forming a self-aligned phase change memory element is provided. A bottom electrode is formed on a landing pad of a phase change memory element. A layer of dielectric material over the bottom electrode and a via etched through the dielectric material to expose the bottom electrode. The via is lined with a GST phase change layer that is etched back from the top surface of the dielectric layer. The via is then filled with a nitride fill, at least of portion of which is etched back from the top surface of the dielectric layer. A top electrode metal is then deposited at the top of the via, wherein the top electrode material is coupled to the phase change material and nitride fill material.

Abstract: Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having self-aligned contacts. In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source/drain region of a substrate. A conductive gate is formed over a channel region of the semiconductor fin. A top source/drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source/drain region. A dielectric cap is formed over the top metallization layer.

Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.