Patents by Inventor Benjamin Chu

Benjamin Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10930500
    Abstract: III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Benjamin Chu-Kung, Marko Radosavljevic, Sanaz K. Gardner, Seung Hoon Sung, Ravi Pillarisetty, Robert S. Chau
  • Publication number: 20210050455
    Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.
    Type: Application
    Filed: October 19, 2020
    Publication date: February 18, 2021
    Inventors: Van H. LE, Gilbert DEWEY, Rafael RIOS, Jack T. KAVALIEROS, Marko RADOSAVLJEVIC, Kent E. MILLARD, Marc C. FRENCH, Ashish AGRAWAL, Benjamin CHU-KUNG, Ryan E. ARCH
  • Publication number: 20210039888
    Abstract: A processing system for processing objects using a programmable motion device is disclosed. The processing system a perception unit for perceiving identifying indicia representative of an identity of an object associated with an input conveyance system, and an acquisition system for acquiring the object from a plurality of objects at an input area using an end effector of the programmable motion device, wherein the programmable motion device is adapted for assisting in the delivery of the object to an identified processing location. The identified processing location being associated with the identifying indicia and said identified processing location being provided as one of a plurality of processing locations. The processing system also includes a delivery system for receiving the object in a carrier and for delivering the object toward the identified processing location.
    Type: Application
    Filed: October 22, 2020
    Publication date: February 11, 2021
    Inventors: Thomas WAGNER, Kevin AHEARN, John Richard AMEND, JR., Benjamin COHEN, Michael DAWSON-HAGGERTY, William Hartman FORT, Christopher GEYER, Jennifer Eileen KING, Thomas KOLETSCHKA, Michael Cap KOVAL, Kyle MARONEY, Matthew T. MASON, William Chu-Hyon MCMAHAN, Gene Temple PRICE, Joseph ROMANO, Daniel SMITH, Siddhartha SRINIVASA, Prasanna VELAGAPUDI, Thomas ALLEN
  • Patent number: 10913612
    Abstract: An automated carrier system is disclosed for moving objects to be processed. The automated carrier system includes a discontinuous plurality of track sections on which an automated carrier may be directed to move, and the automated carrier includes a base structure on which an object may be supported, and at least two wheels assemblies being pivotally supported on the base structure for pivoting movement from a first position to a second position to effect a change in direction of movement of the carrier.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: February 9, 2021
    Assignee: Berkshire Grey, Inc.
    Inventors: Thomas Wagner, Kevin Ahearn, John Richard Amend, Jr., Benjamin Cohen, Michael Dawson-Haggerty, William Hartman Fort, Christopher Geyer, Jennifer Eileen King, Thomas Koletschka, Michael Cap Koval, Kyle Maroney, Matthew T. Mason, William Chu-Hyon McMahan, Gene Temple Price, Joseph Romano, Daniel Smith, Siddhartha Srinivasa, Prasanna Velagapudi, Thomas Allen
  • Patent number: 10910642
    Abstract: A nonaqueous electrolyte composition for use in a redox flow battery system, comprising a nonaqueous supporting electrolyte and a ligand metal complex as an electrochemically active component.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: February 2, 2021
    Assignee: Triad National Security, LLC
    Inventors: Benjamin L. Davis, Terry Chu
  • Patent number: 10906740
    Abstract: A method of processing objects using a programmable motion device is disclosed. The method includes the steps of perceiving identifying indicia representative of an identity of a plurality of objects and directing the plurality of objects toward an input area from at least one input conveyance system, acquiring an object from the plurality of objects at the input area using an end effector of the programmable motion device, and moving the acquired object toward an identified processing location using the programmable motion device, said identified processing location being associated with the identifying indicia and said identified processing location being provided as one of a plurality of processing locations that are radially spaced from the programmable motion device.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: February 2, 2021
    Assignee: Berkshire Grey, Inc.
    Inventors: Thomas Wagner, Kevin Ahearn, John Richard Amend, Jr., Benjamin Cohen, Michael Dawson-Haggerty, William Hartman Fort, Christopher Geyer, Jennifer Eileen King, Thomas Koletschka, Michael Cap Koval, Kyle Maroney, Matthew T. Mason, William Chu-Hyon McMahan, Gene Temple Price, Joseph Romano, Daniel Smith, Siddhartha Srinivasa, Prasanna Velagapudi, Thomas Allen
  • Patent number: 10894838
    Abstract: The present disclosure provides methods for producing carboxylated nanocelluloses. Compared with conventional methods, the methods of the present disclosure are simple and cost-effective in the production of carboxylated (or carboxy) nanocelluloses, in embodiments nanofibers and/or nanowhiskers, directly from raw biomass, including lignocellulose wood, non-wood sources, non-lignocellulose wood, lignocellulose or pure cellulose. The carboxy groups on the surface of nanocellulose thus produced can then be easily modified into functional derivatives such as amide, acetate, ether, ester, etc. The resulting nanocelluloses may be used to form purifying agents and/or filters to remove impurities from wastewater.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: January 19, 2021
    Assignee: The Research Foundation for the State University of New York
    Inventors: Benjamin S. Hsiao, Benjamin Chu, Priyanka R. Sharma
  • Patent number: 10894674
    Abstract: A storage, retrieval and processing system for processing objects is disclosed.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: January 19, 2021
    Assignee: Berkshire Grey, Inc.
    Inventors: Thomas Wagner, Kevin Ahearn, John Richard Amend, Jr., Benjamin Cohen, Michael Dawson-Haggerty, William Hartman Fort, Christopher Geyer, Victoria Hinchey, Jennifer Eileen King, Thomas Koletschka, Michael Cap Koval, Kyle Maroney, Matthew T. Mason, William Chu-Hyon Mcmahan, Gene Temple Price, Joseph Romano, Daniel Smith, Siddhartha Srinivasa, Prasanna Velagapudi, Thomas Allen
  • Publication number: 20210005748
    Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.
    Type: Application
    Filed: September 26, 2017
    Publication date: January 7, 2021
    Applicant: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Cory C. Bomberger, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung, Seung Hoon Sung, Siddharth Chouksey
  • Publication number: 20210005722
    Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent insulator regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, a dopant-rich insulator cap is deposited adjacent to the source and/or drain regions, to provide dopant diffusion reduction. In some embodiments, the dopant-rich insulator cap is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10% by atomic percentage. In some embodiments, the dopant-rich insulator cap may have a thickness in the range of 10 to 100 nanometers and a height in the range of 10 to 200 nanometers.
    Type: Application
    Filed: September 29, 2017
    Publication date: January 7, 2021
    Applicant: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Cory C. Bomberger, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung, Seung Hoon Sung, Siddharth Chouksey
  • Publication number: 20200411690
    Abstract: An apparatus is provided which comprises: a first region over a substrate, wherein the first region comprises a first semiconductor material having a L-valley transport energy band structure, a second region in contact with the first region at a junction, wherein the second region comprises a second semiconductor material having a X-valley transport energy band structure, wherein a <111> crystal direction of one or more crystals of the first and second semiconductor materials are substantially orthogonal to the junction, and a metal adjacent to the second region, the metal conductively coupled to the first region through the junction. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Dax M. Crum, Cory E. Weber, Rishabh Mehandru, Harold Kennel, Benjamin Chu-Kung
  • Publication number: 20200398442
    Abstract: A system including a programmable motion device and an end effector for grasping objects to be moved by the programmable motion device is disclosed. The system includes a vacuum source that provides a high flow vacuum such that an object may be grasped at an end effector opening while permitting a substantial flow of air through the opening, and a dead-head limitation system for limiting any effects of dead-heading on the vacuum source in the event that a flow of air to the vacuum source is interrupted.
    Type: Application
    Filed: September 3, 2020
    Publication date: December 24, 2020
    Inventors: Thomas WAGNER, Kevin Ahearn, John Richard Amend, JR., Benjamin Cohen, Michael Dawson-Haggerty, William Hartman Fort, Christopher Geyer, Jennifer Eileen King, Thomas Koletschka, Michael Cap Koval, Kyle Maroney, Matthew T. Mason, William Chu-Hyon McMahan, Gene Temple Price, Joseph Romano, Daniel Smith, Siddhartha Srinivasa, Prasanna Velagapudi, Thomas Allen
  • Patent number: 10870538
    Abstract: A processing system for processing objects using a programmable motion device is disclosed. The processing system a perception unit for perceiving identifying indicia representative of an identity of an object associated with an input conveyance system, and an acquisition system for acquiring the object from a plurality of objects at an input area using an end effector of the programmable motion device, wherein the programmable motion device is adapted for assisting in the delivery of the object to an identified processing location. The identified processing location being associated with the identifying indicia and said identified processing location being provided as one of a plurality of processing locations. The processing system also includes a delivery system for receiving the object in a carrier and for delivering the object toward the identified processing location.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: December 22, 2020
    Assignee: Berkshire Grey, Inc.
    Inventors: Thomas Wagner, Kevin Ahearn, John Richard Amend, Jr., Benjamin Cohen, Michael Dawson-Haggerty, William Hartman Fort, Christopher Geyer, Jennifer Eileen King, Thomas Koletschka, Michael Cap Koval, Kyle Maroney, Matthew T. Mason, William Chu-Hyon McMahan, Gene Temple Price, Joseph Romano, Daniel Smith, Siddhartha Srinivasa, Prasanna Velagapudi, Thomas Allen
  • Publication number: 20200391250
    Abstract: A processing system including a singulation system is disclosed. The singulation system includes a conveying system for moving objects to be processed from a source area along a first direction, a detection system for detecting objects at the conveying system, and for selecting certain selected objects for redistribution on the conveying system, and a movement redistribution system for redistributing the certain selected objects on the conveying system for providing a singulated stream of objects.
    Type: Application
    Filed: August 20, 2020
    Publication date: December 17, 2020
    Inventors: Thomas Wagner, Kevin Ahearn, John Richard Amend, JR., Benjamin Cohen, William Hartman Fort, Michael Dawson-Haggerty, Christopher Geyer, Jennifer Eileen King, Thomas Koletschka, Michael Cap Koval, Kyle Maroney, Matthew T. Mason, William Chu-Hyon McMahan, Gene Temple Price, Joseph Romano, Daniel Smith, Siddhartha Srinivasa, Prasanna Velagapudi, Thomas Allen
  • Publication number: 20200369470
    Abstract: A storage, retrieval and processing system for processing objects is disclosed. The storage, retrieval and processing system includes a plurality of storage bins providing storage of a plurality of objects, where the plurality of storage bins is in communication with a bin conveyance system for moving selected storage bins to a storage bin processing location, a programmable motion device in communication with the bin processing location for receiving a selected storage bin from the plurality of bins, where the programmable motion device includes an end effector for grasping and moving a selected object out of a selected storage bin, and a plurality of destination bins in communication with the bin conveyance system for moving a selected destination bin from a destination bin processing location that is proximate the programmable motion device to the plurality of destination bins.
    Type: Application
    Filed: August 14, 2020
    Publication date: November 26, 2020
    Inventors: Thomas Wagner, Kevin Ahearn, John Richard Amend, JR., Benjamin Cohen, Michael Dawson-Haggerty, William Hartman Fort, Christopher Geyer, Jennifer Eileen King, Thomas Koletschka, Michael Cap Koval, Kyle Maroney, Matthew T. Mason, William Chu-Hyon McMahan, Gene Temple Price, Joseph Romano, Daniel Smith, Siddhartha Srinivasa, Prasanna Velagapudi, Thomas Allen
  • Patent number: 10847656
    Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Van H. Le, Gilbert Dewey, Rafael Rios, Jack T. Kavalieros, Marko Radosavljevic, Kent E. Millard, Marc C. French, Ashish Agrawal, Benjamin Chu-Kung, Ryan E. Arch
  • Publication number: 20200365711
    Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the STI is doped with an n-type impurity, in regions of the STI adjacent to the source and/or drain regions, to provide dopant diffusion reduction. In some embodiments, the STI region is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10% by atomic percentage. In some embodiments, the thickness of the doped STI region may range between 10 and 100 nanometers.
    Type: Application
    Filed: September 29, 2017
    Publication date: November 19, 2020
    Applicant: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Cory C. Bomberger, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung, Seung Hoon Sung, Siddharth Chouksey
  • Publication number: 20200343379
    Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, a metallic encapsulation layer above the substrate, and a gate electrode above the substrate and next to the metallic encapsulation layer. A channel layer may be above the metallic encapsulation layer and the gate electrode, where the channel layer may include a source area and a drain area. In addition, a source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 27, 2017
    Publication date: October 29, 2020
    Inventors: Abhishek A. SHARMA, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Gilbert DEWEY, Shriram SHIVARAMAN, Inanc MERIC, Benjamin CHU-KUNG
  • Patent number: 10814498
    Abstract: A system including a programmable motion device and an end effector for grasping objects to be moved by the programmable motion device is disclosed. The system includes a vacuum source that provides a high flow vacuum such that an object may be grasped at an end effector opening while permitting a substantial flow of air through the opening, and a dead-head limitation system for limiting any effects of dead-heading on the vacuum source in the event that a flow of air to the vacuum source is interrupted.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: October 27, 2020
    Assignee: Berkshire Grey, Inc.
    Inventors: Thomas Wagner, Kevin Ahearn, John Richard Amend, Jr., Benjamin Cohen, Michael Dawson-Haggerty, William Hartman Fort, Christopher Geyer, Jennifer Eileen King, Thomas Koletschka, Michael Cap Koval, Kyle Maroney, Matthew T. Mason, William Chu-Hyon McMahan, Gene Temple Price, Joseph Romano, Daniel Smith, Siddhartha Srinivasa, Prasanna Velagapudi, Thomas Allen
  • Publication number: 20200335610
    Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.
    Type: Application
    Filed: February 28, 2018
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Cheng-Ying Huang, Jack Kavalieros, Ian Young, Matthew Metz, Willy Rachmady, Uygar Avci, Ashish Agrawal, Benjamin Chu-Kung