Patents by Inventor Benjamin Chu

Benjamin Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190348500
    Abstract: Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements. The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (e.g., B, P, or As) into the adjacent Ge-rich channel region. In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon. Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion. In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region. Numerous embodiments, configurations, and variations will be apparent.
    Type: Application
    Filed: April 1, 2017
    Publication date: November 14, 2019
    Applicant: Intel Corporation
    Inventors: Glenn A. GLASS, Anand S. MURTHY, Karthik JAMBUNATHAN, Benjamin CHU-KUNG, Seung Hoon SUNG, Jack T. KAVALIEROS, Tahir GHANI, Harold W. KENNEL
  • Publication number: 20190348499
    Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 14, 2019
    Inventors: Van H. LE, Benjamin CHU-KUNG, Harold Hal W. KENNEL, Willy RACHMADY, Ravi PILLARISETTY, Jack T. KAVALIEROS
  • Publication number: 20190348415
    Abstract: Techniques are disclosed for forming transistors employing a source/drain (S/D) cap layer for Ge-rich S/D regions to, e.g., help suppress contact metal piping. Contact metal piping occurs when metal material from the S/D contact region diffuses into the channel region, which can lead to a reduction of the effective gate length and can even cause device shorting/failure. The S/D cap layer includes silicon (Si) and/or carbon (C) to help suppress the continuous reaction of contact metal material with the Ge-rich S/D material (e.g., Ge or SiGe with at least 50% Ge concentration by atomic percentage), thereby reducing or preventing the diffusion of metal from the S/D contact region into the channel region as subsequent processing occurs. In addition, the Si and/or C-based S/D cap layer is more selective to contact trench etch than the doped Ge-rich material included in the S/D region, thereby increasing controllability during contact trench etch processing.
    Type: Application
    Filed: March 30, 2017
    Publication date: November 14, 2019
    Applicant: INTEL CORPORATION
    Inventors: SEUNG HOON SUNG, GLENN A. GLASS, HAROLD W. KENNEL, ASHISH AGRAWAL, VAN H. LE, BENJAMIN CHU-KUNG, SIDDHARTH CHOUKSEY, ANAND S. MURTHY, JACK T. KAVALIEROS, TAHIR GHANI
  • Patent number: 10475706
    Abstract: Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystaline defects in the fins due to lattice mismatch in the layer interfaces.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Niti Goel, Benjamin Chu-Kung, Sansaptak Dasgupta, Niloy Mukherjee, Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Robert S. Chau, Ravi Pillarisetty
  • Patent number: 10475888
    Abstract: An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Seung Hoon Sung, Sanaz K. Gardner, Marko Radosavljevic, Benjamin Chu-Kung, Robert S. Chau
  • Publication number: 20190341300
    Abstract: Techniques are disclosed for forming transistors employing a carbon-based etch stop layer (ESL) for preserving source and drain (S/D) material during contact trench etch processing. As can be understood based on this disclosure, carbon-based layers can provide increased resistance for etch processing, such that employing a carbon-based ESL on S/D material can preserve that S/D material during contact trench etch processing. This is due to carbon-based layers being able to provide more robust (e.g., more selective) etch selectivity during contact trench etch processing than the S/D material it is preserving (e.g., Si, SiGe, Ge, group III-V semiconductor material) and other etch stop layers (e.g., insulator material-based etch stop layers). Employing a carbon-based ESL enables a given S/D region to protrude from shallow trench isolation (STI) material prior to contact metal deposition, thereby providing more surface area for making contact to the given S/D region, which improves transistor performance.
    Type: Application
    Filed: March 30, 2017
    Publication date: November 7, 2019
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, ANAND S. MURTHY, KARTHIK JAMBUNATHAN, BENJAMIN CHU-KUNG, SEUNG HOON SUNG, JACK T. KAVALIEROS, TAHIR GHANI
  • Publication number: 20190337723
    Abstract: A processing system for processing objects using a programmable motion device is disclosed. The processing system a perception unit for perceiving identifying indicia representative of an identity of an object associated with an input conveyance system, and an acquisition system for acquiring the object from a plurality of objects at an input area using an end effector of the programmable motion device, wherein the programmable motion device is adapted for assisting in the delivery of the object to an identified processing location. The identified processing location being associated with the identifying indicia and said identified processing location being provided as one of a plurality of processing locations. The processing system also includes a delivery system for receiving the object in a carrier and for delivering the object toward the identified processing location.
    Type: Application
    Filed: May 4, 2018
    Publication date: November 7, 2019
    Inventors: Thomas WAGNER, Kevin AHEARN, John Richard AMEND, JR., Benjamin COHEN, Michael DAWSON-HAGGERTY, William Hartman FORT, Christopher GEYER, Jennifer Eileen KING, Thomas KOLETSCHKA, Michael Cap KOVAL, Kyle MARONEY, Matthew T. MASON, William Chu-Hyon MCMAHAN, Gene Temple PRICE, Joseph ROMANO, Daniel SMITH, Siddhartha SRINIVASA, Prasanna VELAGAPUDI, Thomas ALLEN
  • Publication number: 20190341453
    Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a drain region of doped semiconductor material on the substrate adjacent a second side of the semiconductor region, and a transition region in the drain region, adjacent the semiconductor region, wherein the transition region comprises varying dopant concentrations that increase in a direction away from the semiconductor region. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 31, 2016
    Publication date: November 7, 2019
    Applicant: Intel Corporation
    Inventors: Seung Hoon Sung, Dipanjan Basu, Glenn A. Glass, Harold W. Kennel, Ashish Agrawal, Benjamin Chu-Kung, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 10438034
    Abstract: A space efficient automated processing system for processing objects is disclosed.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: October 8, 2019
    Assignee: Berkshire Grey, Inc.
    Inventors: Thomas Wagner, Kevin Ahearn, John Richard Amend, Jr., Benjamin Cohen, Michael Dawson-Haggerty, William Hartman Fort, Christopher Geyer, Victoria Hinchey, Jennifer Eileen King, Thomas Koletschka, Michael Cap Koval, Kyle Maroney, Matthew T. Mason, William Chu-Hyon McMahan, Gene Temple Price, Joseph Romano, Daniel Smith, Siddhartha Srinivasa, Prasanna Velagapudi, Thomas Allen
  • Publication number: 20190305137
    Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Shriram Shivaraman, Benjamin Chu-Kung, Yih Wang, Tahir Ghani
  • Publication number: 20190305085
    Abstract: An integrated circuit structure includes: a semiconductor nanowire extending in a length direction and including a body portion; a gate dielectric surrounding the body portion; a gate electrode insulated from the body portion by the gate dielectric; a semiconductor source portion adjacent to a first side of the body portion; and a semiconductor drain portion adjacent to a second side of the body portion opposite the first side, the narrowest dimension of the second side of the body portion being smaller than the narrowest dimension of the first side. In an embodiment, the nanowire has a conical tapering. In an embodiment, the gate electrode extends along the body portion in the length direction to the source portion, but not to the drain portion. In an embodiment, the drain portion at the second side of the body portion has a lower dopant concentration than the source portion at the first side.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Applicant: INTEL CORPORATION
    Inventors: Seung Hoon Sung, Dipanjan Basu, Ashish Agrawal, Benjamin Chu-Kung, Siddharth Chouksey, Cory C. Bomberger, Tahir Ghani, Anand S. Murthy, Jack T. Kavalieros
  • Publication number: 20190304982
    Abstract: A method is described. The method includes forming bit line structures above bitline contact structures, forming a first material on top surfaces and sidewall surfaces of the bit line structures to establish step structures for via formation, and forming a second material on the top surface of the first material. Capacitor landing structures are formed by patterning the second material.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Abhishek A. SHARMA, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Yih WANG, Benjamin CHU-KUNG, Shriram SHIVARAMAN
  • Publication number: 20190305101
    Abstract: Techniques and mechanisms for improved performance characteristics of a transistor device. In an embodiment, a transistor of an integrated circuit comprises a source, a drain, a gate, a gate dielectric and a semiconductor structure which adjoins the gate dielectric. The semiconductor structure is configured to provide a conductive channel between the source and drain. The semiconductor structure includes first, second and third portions, the second portion between the source and the gate, and the third portion between the drain and the gate, wherein the first portion connects the second portion and third portion to one another. A thickness of the first portion is less than another thickness of one of the second portion or the third portion. In another embodiment, the locations of thicker portions of semiconductor structure mitigate overall transistor capacitance, while a thinner intermediary portion of the semiconductor structure promotes good sub-threshold swing characteristics.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Sean T. Ma, Jack Kavalieros, Benjamin Chu-Kung
  • Publication number: 20190287789
    Abstract: III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.
    Type: Application
    Filed: June 4, 2019
    Publication date: September 19, 2019
    Applicant: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Benjamin Chu-Kung, Marko Radosavljevic, Sanaz K. Gardner, Seung Hoon Sung, Ravi Pillarisetty, Robert S. Chau
  • Publication number: 20190273133
    Abstract: Disclosed herein are transistor amorphous interlayer arrangements, and related methods and devices. For example, in some embodiments, transistor amorphous interlayer arrangement may include a channel material and a transistor source/drain stack. The transistor source/drain stack may include a transistor electrode material configured to be a transistor source/drain contact, i.e. either a source contact or a drain contact of the transistor, and a doped amorphous semiconductor material disposed between the transistor electrode material and the channel material.
    Type: Application
    Filed: December 14, 2016
    Publication date: September 5, 2019
    Applicant: Intel Corporation
    Inventors: Ashish Agrawal, Benjamin Chu-Kung, Seung Hoon Sung, Siddharth Chouksey, Glenn A. Glass, Van H. Le, Anand S. Murthy, Jack T. Kavalieros, Matthew V. Metz, Willy Rachmady
  • Patent number: 10403733
    Abstract: Embodiments of the present disclosure describe semiconductor devices comprised of a semiconductor substrate with a metal oxide semiconductor field effect transistor having a channel including germanium or silicon-germanium, where a dielectric layer is coupled to the channel. The dielectric layer may include a metal oxide and at least one additional element, where the at least one additional element may increase a band gap of the dielectric layer. A gate electrode may be coupled to the dielectric layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Ashish Agrawal, Benjamin Chu-Kung, Van H. Le, Matthew V. Metz, Willy Rachmady, Jack T. Kavalieros, Rafael Rios
  • Patent number: 10388733
    Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Van H. Le, Benjamin Chu-Kung, Harold Hal W. Kennel, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros
  • Patent number: 10373977
    Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: August 6, 2019
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung, Chandra S. Mohapatra, Karthik Jambunathan, Gilbert Dewey, Willy Rachmady
  • Publication number: 20190229022
    Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
    Type: Application
    Filed: April 1, 2019
    Publication date: July 25, 2019
    Inventors: Marko RADOSAVLJEVIC, Ravi PILLARISETTY, Gilbert DEWEY, Niloy MUKHERJEE, Jack KAVALIEROS, Willy RACHMADY, Van LE, Benjamin CHU-KUNG, Matthew METZ, Robert CHAU
  • Publication number: 20190217471
    Abstract: A programmable motion system is disclosed that includes a dynamic end effector system. The dynamic end effector system includes a plurality of acquisition units that are provided at an exchange station within an area accessible by the programmable motion device, and a coupling system for coupling any of the plurality of acquisition units to an end effector of the programmable motion device such that any of the acquisition units may be automatically selected from the exchange station and used by the programmable motion device without requiring any activation or actuation by the exchange station and without requiring any intervention by a human.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 18, 2019
    Inventors: Joseph ROMANO, William Chu-Hyon MCMAHAN, Benjamin COHEN, Andrew GAUTHIER, Matthew T. MASON, Thomas WAGNER, Prasanna VELAGAPUDI, Michael DAWSON-HAGGERTY