Abstract: An automated carrier system is disclosed for moving objects to be processed. The automated carrier system includes a discontinuous plurality of track sections on which an automated carrier may be directed to move, and the automated carrier includes a base structure on which an object may be supported, and at least two wheels assemblies being pivotally supported on the base structure for pivoting movement from a first position to a second position to effect a change in direction of movement of the carrier.

Abstract: A system is disclosed for providing high flow vacuum control to an end-effector of a programmable motion device. The system includes a vacuum source for providing a high flow vacuum, a conduit path leading from the end-effector to the high flow vacuum source, a sensor system for sensing any of a pressure or a flow at any of the end-effector, the conduit path, and the vacuum source, and providing sensor information, and a pneumatic control module including a vacuum pressure adjustment system for adjusting the high flow vacuum within the conduit path responsive to the sensor information.

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless communication device (WCD) may communicate, via a wireless link, with an audio device using a first configuration having first values for communication parameters. The WCD may transmit an indication to switch to a second configuration based at least in part on a configuration switch trigger, the configuration switch trigger being based at least in part on one or more of a link quality metric associated with the wireless link or a change of a use state of the WCD, and the second configuration having second values for the communication parameters associated with a reduction in voltage-induced interference in an audio output of the audio device. Numerous other aspects are described.

Abstract: A heart rate monitor may include a strap and a heart rate monitoring pod releasably coupled to the strap. A securement element may be disposed in the strap to selectively secure the pod to the strap. The pod may be selectively removable from the securement element and include one or more charger contacts. The pod may include one or more LEDs and/or vibrating elements to provide a light animation feedback and/or a haptic feedback to a user. A charger may be provided to charge the pod. The charger and pod may have complementary shapes to align the pod on the charger. For example, placement of the pod on the charger may align the charger contacts of the pod with one or more charging elements (e.g., pins) disposed in the charger.

Abstract: A storage, retrieval and processing system for processing objects is disclosed. The storage, retrieval and processing system includes a plurality of storage bins providing storage of a plurality of objects, where the plurality of storage bins is in communication with a retrieval conveyance system, a programmable motion device in communication with the retrieval conveyance system for receiving the storage bins from the plurality of bins, where the programmable motion device includes an end effector for grasping and moving a selected object out of a selected storage bin, and a movable carriage for receiving the selected object from the end effector of the programmable motion device, and for carrying the selected object to one of a plurality of destination bins.

Abstract: A system for providing variable opacity includes a polarization assembly disposed at a vehicle. The polarization assembly includes a first panel having a plurality of first polarizing elements, and a second panel having a plurality of second polarizing elements, the first panel and the second panel overlapping in a path of light incident on the vehicle. The system also includes an actuation device configured to linearly translate the first panel relative to the second panel between a first position in which the polarization assembly is transparent to the light and a second position in which the polarization assembly at least partially blocks the light.

Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.

Abstract: Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.

Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.

Abstract: Techniques are disclosed for forming thin-film transistors (TFTs) with low contact resistance. As disclosed in the present application, the low contact resistance can be achieved by intentionally thinning one or both of the source/drain (S/D) regions of the thin-film layer of the TFT device. As the TFT layer may have an initial thickness in the range of 20-65 nm, the techniques for thinning the S/D regions of the TFT layer described herein may reduce the thickness in one or both of those S/D regions to a resulting thickness of 3-10 nm, for example. Intentionally thinning one or both of the S/D regions of the TFT layer induces more electrostatic charges inside the thinned S/D region, thereby increasing the effective dopant in that S/D region. The increase in effective dopant in the thinned S/D region helps lower the related contact resistance, thereby leading to enhanced overall device performance.

Abstract: Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.

Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.

Abstract: Disclosed herein are transistors with ferroelectric gates, and related methods and devices. For example, in some embodiments, a transistor may include a channel material, and a gate stack, and the gate stack may include a gate electrode material and a ferroelectric material between the gate electrode material and the channel material.

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.

Abstract: A method is described. The method includes forming bit line structures above bitline contact structures, forming a first material on top surfaces and sidewall surfaces of the bit line structures to establish step structures for via formation, and forming a second material on the top surface of the first material. Capacitor landing structures are formed by patterning the second material.

Abstract: An embodiment includes an apparatus comprising: a substrate; a thin film transistor (TFT) comprising: source, drain, and gate contacts; a semiconductor material, comprising a channel, between the substrate and the gate contact; a gate dielectric layer between the gate contact and the channel; and an additional layer between the channel and the substrate; wherein (a)(i) the channel includes carriers selected from the group consisting of hole carriers or electron carriers, (a)(ii) the additional layer includes an insulator material that includes charged particles having a polarity equal to a polarity of the carriers. Other embodiments are described herein.

Abstract: Systems and methods of improved network analytics are disclosed. A system may determine feature propagation in a network of nodes of a graph database. The system may compute, at scale, datasets having complex relationships using graph analysis to determine network effects of entities in a network of entities stored in a graph database. The system may identify entities of interest, which may be associated with a quantitative feature value. The system may compute paths from an entity to the entities of interest, centrality metrics for entities in each of the paths, and path lengths to determine network effects of the entity of interests on the entity. The system may use the computed network effects, taking into account types of relationships between entities in the paths, to determine scaled quantitative feature values for the entity that is subject to the network effects of the entities of interest.