Patents by Inventor Benjamin Chu

Benjamin Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10748993
    Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Van H. Le, Benjamin Chu-Kung, Harold Hal W. Kennel, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros
  • Publication number: 20200258982
    Abstract: Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.
    Type: Application
    Filed: December 26, 2017
    Publication date: August 13, 2020
    Applicant: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Cory C. Bomberger, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung, Seung Hoon Sung, Siddharth Chouksey
  • Patent number: 10734488
    Abstract: Embodiments related to transistors and integrated circuits having aluminum indium phosphide subfins and germanium channels, systems incorporating such transistors, and methods for forming them are discussed.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Matthew V. Metz, Willy Rachmady, Harold W. Kennel, Van H. Le, Benjamin Chu-Kung, Jack T. Kavalieros, Gilbert Dewey
  • Patent number: 10734511
    Abstract: An embodiment includes a field effect transistor, comprising: a source region comprising a first III-V material doped to a first conductivity type; a drain region comprising a second III-V material doped to a second conductivity type that is opposite the first conductivity type; a gate electrode disposed over a channel region comprising a third III-V material; and a first spacer, between the channel and drain regions, comprising a fourth III-V material having a charge carrier-blocking band offset from the third III-V material. Other embodiments are described herein.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Willy Rachmady, Jack T. Kavalieros, Matthew V. Metz, Benjamin Chu-Kung, Gilbert Dewey, Rafael Rios
  • Patent number: 10727339
    Abstract: Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain region is disposed on the vertical channel region and has a second width parallel with and substantially greater than the first width. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Gilbert Dewey, Van H. Le, Jack T. Kavalieros, Marko Radosavljevic, Ravi Pillarisetty, Han Wui Then, Niloy Mukherjee, Sansaptak Dasgupta
  • Patent number: 10727138
    Abstract: A monocrystalline semiconductor layer is formed on a conductive layer on an insulating layer on a substrate. The conductive layer is a part of an interconnect layer. The monocrystalline semiconductor layer extends laterally on the insulating layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Van H. Le, Marko Radosavljevic, Benjamin Chu-Kung, Rafael Rios, Gilbert Dewey
  • Publication number: 20200235246
    Abstract: Techniques are disclosed for forming thin-film transistors (TFTs) with low contact resistance. As disclosed in the present application, the low contact resistance can be achieved by intentionally thinning one or both of the source/drain (S/D) regions of the thin-film layer of the TFT device. As the TFT layer may have an initial thickness in the range of 20-65 nm, the techniques for thinning the S/D regions of the TFT layer described herein may reduce the thickness in one or both of those S/D regions to a resulting thickness of 3-10 nm, for example. Intentionally thinning one or both of the S/D regions of the TFT layer induces more electrostatic charges inside the thinned S/D region, thereby increasing the effective dopant in that S/D region. The increase in effective dopant in the thinned S/D region helps lower the related contact resistance, thereby leading to enhanced overall device performance.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 23, 2020
    Applicant: INTEL CORPORATION
    Inventors: Abhishek A. Sharma, Van H. Le, Li Huey Tan, Tristan A. Tronic, Benjamin Chu-Kung, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 10717381
    Abstract: A tie down anchor tension monitoring system includes a tension level monitoring module and at least one tie down anchoring point integrated into a cargo carrying space configured for connecting to a free end of a cargo tie down strap. The system further includes at least one tension level monitoring sensor integrated with the at least one tie down anchoring point, wherein the at least one tension monitoring sensor is configured to output a signal to the tension monitoring module that is indicative of a tension level of the cargo tie down strap.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: July 21, 2020
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventor: Benjamin Chu
  • Publication number: 20200227568
    Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 16, 2020
    Inventors: Van H. LE, Abhishek A. SHARMA, Benjamin CHU-KUNG, Gilbert DEWEY, Ravi PILLARISETTY, Miriam R. RESHOTKO, Shriram SHIVARAMAN, Li Huey TAN, Tristan A. TRONIC, Jack T. KAVALIEROS
  • Patent number: 10702815
    Abstract: Membranes suitable for use in membrane distillation are provided. Such membranes may include nano-fibrous layers with adjustable pore sizes. The membranes may include a hydrophobic nano fibrous scaffold and a thin hydrophilic protecting layer that can significantly reduce fouling and scaling problems.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: July 7, 2020
    Assignee: The Research Foundation for the State University of New York
    Inventors: Benjamin Chu, Benjamin S. Hsiao
  • Publication number: 20200212186
    Abstract: Embodiments related to transistors and integrated circuits having aluminum indium phosphide subfins and germanium channels, systems incorporating such transistors, and methods for forming them are discussed.
    Type: Application
    Filed: September 11, 2015
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Matthew V. Metz, Willy Rachmady, Harold W. Kennel, Van H. Le, Benjamin Chu-Kung, Jack T. Kavalieros, Gilbert Dewey
  • Patent number: 10693008
    Abstract: An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Marko Radosavljevic, Jack T. Kavalieros, Ravi Pillarisetty, Niti Goel, Van H. Le, Gilbert Dewey, Benjamin Chu-Kung
  • Patent number: 10692973
    Abstract: Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements. The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (e.g., B, P, or As) into the adjacent Ge-rich channel region. In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon. Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion. In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region. Numerous embodiments, configurations, and variations will be apparent.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: June 23, 2020
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Benjamin Chu-Kung, Seung Hoon Sung, Jack T. Kavalieros, Tahir Ghani, Harold W. Kennel
  • Publication number: 20200185504
    Abstract: An embodiment includes an apparatus comprising: a substrate; a thin film transistor (TFT) comprising: source, drain, and gate contacts; a semiconductor material, comprising a channel, between the substrate and the gate contact; a gate dielectric layer between the gate contact and the channel; and an additional layer between the channel and the substrate; wherein (a)(i) the channel includes carriers selected from the group consisting of hole carriers or electron carriers, (a)(ii) the additional layer includes an insulator material that includes charged particles having a polarity equal to a polarity of the carriers. Other embodiments are described herein.
    Type: Application
    Filed: September 27, 2017
    Publication date: June 11, 2020
    Inventors: Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Gilbert Dewey, Shriram Shivaraman, Sean T. Ma, Benjamin Chu-Kung
  • Publication number: 20200168724
    Abstract: Disclosed herein are tunneling field effect transistors (TFETs), and related methods and computing devices. In some embodiments, a TFET may include: a first source/drain material having a p-type conductivity; a second source/drain material having an n-type conductivity; a channel material at least partially between the first source/drain material and the second source/drain material, wherein the channel material has a first side face and a second side face opposite the first side face; and a gate above the channel material, on the first side face, and on the second side face.
    Type: Application
    Filed: August 18, 2017
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: Cheng-Ying Huang, Willy Rachmady, Matthew V. Metz, Ashish Agrawal, Benjamin Chu-Kung, Uygar E. Avci, Jack T. Kavalieros, Ian A. Young
  • Patent number: 10665688
    Abstract: An apparatus including a substrate; a transistor device on the substrate including a channel and a source and a drain disposed between the channel; a source contact coupled to the source and a drain contact coupled to the drain; and the source and drain each including a composition including a concentration of germanium at an interface with the channel that is greater than a concentration of germanium at a junction with the source contact. A method including defining an area on a substrate for a transistor device; forming a source and a drain each including an interface with the channel; and forming a contact to one of the source and the drain, wherein a composition of each of the source and the drain includes a concentration of germanium at an interface with the channel that is greater than a concentration at a junction with the contact.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Matthew V. Metz, Benjamin Chu-Kung, Van H. Le, Gilbert Dewey, Ashish Agrawal, Jack T. Kavalieros
  • Publication number: 20200160121
    Abstract: Systems and methods of improved network analytics are disclosed. A system may determine feature propagation in a network of nodes of a graph database. The system may compute, at scale, datasets having complex relationships using graph analysis to determine network effects of entities in a network of entities stored in a graph database. The system may identify entities of interest, which may be associated with a quantitative feature value. The system may compute paths from an entity to the entities of interest, centrality metrics for entities in each of the paths, and path lengths to determine network effects of the entity of interests on the entity. The system may use the computed network effects, taking into account types of relationships between entities in the paths, to determine scaled quantitative feature values for the entity that is subject to the network effects of the entities of interest.
    Type: Application
    Filed: November 15, 2019
    Publication date: May 21, 2020
    Applicant: REFINITIV US ORGANIZATION LLC
    Inventors: Sanjna Balkrishna PARASRAMPURIA, Benjamin Chu MIN XIAN, Thibaut Patrick Marc Michel TIBERGHIEN
  • Patent number: 10644112
    Abstract: A subfin leakage problem with respect to the silicon-germanium (SiGe)/shallow trench isolation (STI) interface can be mitigated with a halo implant. A halo implant is used to form a highly resistive layer. For example, a silicon substrate layer 204 is coupled to a SiGe layer, which is coupled to a germanium (Ge) layer. A gate is disposed on the Ge layer. An implant is implanted in the Ge layer that causes the layer to become more resistive. However, an area does not receive the implant due to being protected (or covered) by the gate. The area remains less resistive than the remainder of the Ge layer. In some embodiments, the resistive area of a Ge layer can be etched and/or an undercuttage (etch undercut or EUC) can be performed to expose the unimplanted Ge area of the Ge layer.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Van Le, Seung Hoon Sung, Jack Kavalieros, Ashish Agrawal, Harold Kennel, Siddharth Chouksey, Anand Murthy, Tahir Ghani, Glenn Glass, Cheng-Ying Huang
  • Patent number: 10644111
    Abstract: An embodiment includes a device comprising: a substrate; a dielectric layer on the substrate and including a trench; a first portion of the trench including a first material that comprises at least one of a group III-V material and a group IV material; and a second portion of the trench, located between the first portion and the substrate, which includes a second material and an upper region and a lower region; wherein: (a)(i) the second material in the upper region has fewer defects than the second material in the lower region, and (a)(ii) the first material is strained. Other embodiments are described herein.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Van H. Le, Ashish Agrawal, Jack T. Kavalieros, Matthew V. Metz, Seung Hoon Sung, Rafael Rios, Gilbert Dewey
  • Publication number: 20200105892
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT). The transistor includes a source electrode oriented in a horizontal direction, and a channel layer in contact with a portion of the source electrode and oriented in a vertical direction substantially orthogonal to the horizontal direction. A gate dielectric layer conformingly covers a top surface of the source electrode and surfaces of the channel layer. A gate electrode conformingly covers a portion of the gate dielectric layer. A drain electrode is above the channel layer, oriented in the horizontal direction. A current path is to include a current portion from the source electrode along a gated region of the channel layer under the gate electrode in the vertical direction, and a current portion along an ungated region of the channel layer in the horizontal direction from the gate electrode to the drain electrode. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Nazila HARATIPOUR, Tahir GHANI, Jack T. KAVALIEROS, Gilbert DEWEY, Benjamin CHU-KUNG, Seung Hoon SUNG, Van H. LE, Shriram SHIVARAMAN, Abhishek SHARMA