Patents by Inventor Benjamin Chu

Benjamin Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200098657
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a conductive contact stack above the substrate and in contact with the channel layer, and a gate electrode separated from the channel layer by a gate dielectric layer. The conductive contact stack may be a drain electrode or a source electrode. In detail, the conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the conductive contact stack. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Arnab SEN GUPTA, Matthew METZ, Benjamin CHU-KUNG, Abhishek SHARMA, Van H. LE, Miriam R. RESHOTKO, Christopher J. JEZEWSKI, Ryan ARCH, Ande KITAMURA, Jack T. KAVALIEROS, Seung Hoon SUNG, Lawrence WONG, Tahir GHANI
  • Publication number: 20200099685
    Abstract: Systems, methods, and apparatuses for implementing authentication of a user login to an external website from a community in a cloud based computing environment. An exemplary system having at least a processor and a memory therein includes means for identifying a first domain where a user is to be allowed to login to an external web page hosted thereon, and means for connecting the external web page with a community of a cloud computing environment hosted on a second domain different than the identified first domain, the connecting means handling how the connected community authenticates the user when the user logs into the external web page and providing one of a plurality of login experiences for the user based on conditions determined at run time.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Inventors: Albert Wijaya, Benjamin Chu, William Charles Mortimore, JR., Ian Glazer, Matthew Bahrenburg, Prashanth Mahalingam Ganesan, Puneet Dhaliwal
  • Publication number: 20200098874
    Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: Justin WEBER, Harold KENNEL, Abhishek SHARMA, Christopher JEZEWSKI, Matthew V. METZ, Tahir GHANI, Jack T. KAVALIEROS, Benjamin CHU-KUNG, Van H. LE, Arnab SEN GUPTA
  • Publication number: 20200098875
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Seung Hoon SUNG, Justin WEBER, Matthew METZ, Arnab SEN GUPTA, Abhishek SHARMA, Benjamin CHU-KUNG, Gilbert DEWEY, Charles KUO, Nazila HARATIPOUR, Shriram SHIVARAMAN, Van H. LE, Tahir GHANI, Jack T. KAVALIEROS, Sean MA
  • Publication number: 20200098926
    Abstract: Disclosed herein are transistors with ferroelectric gates, and related methods and devices. For example, in some embodiments, a transistor may include a channel material, and a gate stack, and the gate stack may include a gate electrode material and a ferroelectric material between the gate electrode material and the channel material.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Ravi Pillarisetty, Brian S. Doyle, Elijah V. Karpov, Prashant Majhi, Gilbert W. Dewey, Benjamin Chu-Kung, Van H. Le, Jack T. Kavalieros, Tahir Ghani
  • Publication number: 20200098931
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a first metal electrode located in a first metal layer is coupled to a first portion of the channel layer by a first short via, and a second metal electrode located in a second metal layer is coupled to a second portion of the channel layer by a second short via. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Abhishek SHARMA, Nazila HARATIPOUR, Seung Hoon SUNG, Benjamin CHU-KUNG, Gilbert DEWEY, Shriram SHIVARAMAN, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Matthew V. METZ, Arnab SEN GUPTA
  • Publication number: 20200098930
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a source electrode or a drain electrode is above or below the channel layer, separated from the gate electrode, and in contact with a portion of the channel layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: Van H. LE, Tahi GHANI, Jack T. KAVALIEROS, Gilbert DEWEY, Matthew METZ, Miriam RESHOTKO, Benjamin CHU-KUNG, Shriram SHIVARAMAN, Abhishek SHARMA, NAZILA HARATIPOUR
  • Publication number: 20200091274
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a gate dielectric layer adjacent to the channel layer, and a gate electrode separated from the channel layer by the gate dielectric layer. The gate dielectric layer includes a non-linear gate dielectric material. The gate electrode, the channel layer, and the gate dielectric layer form a non-linear capacitor. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 19, 2020
    Inventors: Abhishek SHARMA, Ravi PILLARISETTY, Brian DOYLE, Elijah KARPOV, Prashant MAJHI, Gilbert DEWEY, Benjamin CHU-KUNG, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI
  • Publication number: 20200083354
    Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a cap region on the substrate adjacent a second side of the semiconductor region, wherein the cap region comprises semiconductor material of a higher band gap than the semiconductor region, and a drain region comprising doped semiconductor material on the cap region. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 31, 2016
    Publication date: March 12, 2020
    Applicant: Intel Corporation
    Inventors: Seung Hoon SUNG, Dipanjan BASU, Ashish AGRAWAL, Van H. LE, Benjamin CHU-KUNG, Harold W. KENNEL, Glenn A. GLASS, Anand S. MURTHY, Jack T. KAVALIEROS, Tahir GHANI
  • Publication number: 20200083225
    Abstract: Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 12, 2020
    Applicant: Intel Corporation
    Inventors: Sean T. Ma, Aaron D. Lilak, Abhishek A. Sharma, Van H. Le, Seung Hoon Sung, Gilbert W. Dewey, Benjamin Chu-Kung, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 10580882
    Abstract: Embodiments of the present invention are directed to low band gap channel semiconductor devices. In an example, a device includes a first semiconductor material formed above a substrate, the first semiconductor material having a first band gap. A gate dielectric layer is on a surface of the first semiconductor material. A gate electrode is on the gate dielectric layer. A pair of source/drain regions is on opposite sides of the gate electrode. A channel is disposed in the first semiconductor material between the pair of source/drain regions and beneath the gate electrode. The pair of source/drain regions includes a second semiconductor material having a second band gap, and a third semiconductor material having a third band gap. The second semiconductor material is between the first semiconductor material and the third semiconductor material, and the second band gap is greater than the first bandgap.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Jack T. Kavalieros, Willy Rachmady, Matthew V. Metz, Van H. Le, Seiyon Kim, Benjamin Chu-Kung
  • Patent number: 10580895
    Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Robert S. Chau, Sansaptak Dasgupta, Marko Radosavljevic, Benjamin Chu-Kung, Seung Hoon Sung, Sanaz Gardner, Ravi Pillarisetty
  • Publication number: 20200066515
    Abstract: An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germanium; and a seed layer disposed on the substrate between the buffer layer and the substrate, wherein the seed layer includes germanium. A method including forming seed layer on a silicon substrate, wherein the seed layer includes germanium; forming a buffer layer on the seed layer, wherein the buffer layer includes silicon germanium; and forming a transistor device including a channel on the buffer layer.
    Type: Application
    Filed: July 2, 2016
    Publication date: February 27, 2020
    Inventors: Van H. LE, Benjamin CHU-KUNG, Willy RACHMADY, Marc C. FRENCH, Seung Hoon SUNG, Jack T. KAVALIEROS, Matthew V. METZ, Ashish AGRAWAL
  • Patent number: 10573717
    Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Niti Goel, Gilbert Dewey, Niloy Mukherjee, Matthew V. Metz, Marko Radosavljevic, Benjamin Chu-Kung, Jack T. Kavalieros, Robert S. Chau
  • Patent number: 10556222
    Abstract: Water filtration membranes are provided. Such membranes include polysaccharide fibers that have been modified to possess thiol groups thereon, resulting in materials that effectively bind heavy metal ions. The resulting fibers may be used by themselves or applied to a scaffold to form a membrane suitable for removing heavy metals from water, including groundwater.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: February 11, 2020
    Assignee: The Research Foundation for the State University of New York
    Inventors: Robert B. Grubbs, Benjamin S. Hsiao, Benjamin Chu, Rui Yang
  • Publication number: 20200031269
    Abstract: A tie down anchor tension monitoring system includes a tension level monitoring module and at least one tie down anchoring point integrated into a cargo carrying space configured for connecting to a free end of a cargo tie down strap. The system further includes at least one tension level monitoring sensor integrated with the at least one tie down anchoring point, wherein the at least one tension monitoring sensor is configured to output a signal to the tension monitoring module that is indicative of a tension level of the cargo tie down strap.
    Type: Application
    Filed: July 27, 2018
    Publication date: January 30, 2020
    Inventor: Benjamin Chu
  • Publication number: 20200035839
    Abstract: Disclosed herein are transistor gate-channel arrangements that may be implemented in nanowire thin film transistors (TFTs) with textured semiconductors, and related methods and devices. An example transistor gate-channel arrangement may include a substrate, a channel material that includes a textured thin film semiconductor material shaped as a nanowire, a gate dielectric that at least partially wraps around the nanowire, and a gate electrode material that wraps around the gate dielectric. Implementing textured thin film semiconductor channel materials shaped as a nanowire and having a gate stack of a gate dielectric and a gate electrode material wrapping around the nanowire advantageously allows realizing gate all-around or bottom-gate transistor architectures for TFTs with textured semiconductor channel materials.
    Type: Application
    Filed: July 24, 2018
    Publication date: January 30, 2020
    Applicant: Intel Corporation
    Inventors: Shriram Shivaraman, Van H. Le, Abhishek A. Sharma, Gilbert W. Dewey, Benjamin Chu-Kung, Miriam R. Reshotko, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 10541305
    Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: January 21, 2020
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Robert Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Marko Radosavljevic
  • Patent number: 10532322
    Abstract: Elastic microfiltration membranes are provided. These membranes may be used in a membrane bioreactor. Due to the elastic nature of the membranes, removal of fouling materials is improved, thereby increasing the efficiency and longevity of the membranes. Methods for forming such membranes and uses of the membranes are also provided, including their use in membrane bioreactors.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: January 14, 2020
    Assignee: The Research Foundation for the State University of New York
    Inventors: Benjamin Chu, Benjamin S. Hsiao, Ying Su
  • Publication number: 20200006570
    Abstract: Embodiments of the present disclosure are contact structures for thin film transistor (TFT) devices. One embodiment is a TFT device comprising: a substrate; a gate formed above the substrate; a TFT channel formed above the substrate; and a pair of contacts formed on the TFT channel, wherein each of the contacts comprises one or more layers including: a metal that is non-reactive with a material of the TFT channel; or a plurality of layers including a first metal layer formed on a second layer, the second layer in contact with the TFT channel and between the first mater layer and the TFT channel. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Van H. LE, Rajat PAUL, Abhishek SHARMA, Tahir GHANI, Jack KAVALIEROS, Gilbert DEWEY, Matthew METZ, Miriam RESHOTKO, Benjamin CHU-KUNG, Justin WEBER, Shriram SHIVARAMAN