Patents by Inventor Benjamin Chu

Benjamin Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • GE AND III-V CHANNEL SEMICONDUCTOR DEVICES HAVING MAXIMIZED COMPLIANCE AND FREE SURFACE RELAXATION
    Publication number: 20170125524
    Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.
    Type: Application
    Filed: January 12, 2017
    Publication date: May 4, 2017
    Applicants: Intel Corporation, Intel Corporation
    Inventors: RAVI PILLARISETTY, SANSAPTAK DASGUPTA, NITI GOEL, VAN H. LE, MARKO RADOSAVLJEVIC, GILBERT DEWEY, NILOY MUKHERJEE, MATTHEW V. METZ, WILLY RACHMADY, JACK T. KAVALIEROS, BENJAMIN CHU-KUNG, HAROLD W. KENNEL, STEPHEN M. CEA, ROBERT S. CHAU
  • GERMANIUM TIN CHANNEL TRANSISTORS
    Publication number: 20170125527
    Abstract: Techniques related to transistors and integrated circuits having germanium tin, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a channel region that comprises a germanium tin portion of a fin such that the fin includes a buffer layer disposed over a substrate and the germanium tin portion disposed over the buffer layer.
    Type: Application
    Filed: March 27, 2014
    Publication date: May 4, 2017
    Inventors: Ravi Pillarisetty, Van H. Le, Willy Rachmady, Roza Kotlyar, Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Gilbert Dewey, Benjamin Chu-Kung, Jack T. Kavalieros
  • Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy
    Patent number: 9640537
    Abstract: A single fin or a pair of co-integrated n- and p- type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Niti Goel, Robert S. Chau, Jack T. Kavalieros, Benjamin Chu-Kung, Matthew V. Metz, Niloy Mukherjee, Nancy M. Zelick, Gilbert Dewey, Willy Rachmady, Marko Radosavljevic, Van H. Le, Ravi Pillarisetty, Sansaptak Dasgupta
  • Deep gate-all-around semiconductor device having germanium or group III-V active layer
    Patent number: 9640671
    Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
  • Selective epitaxially grown III-V materials based devices
    Patent number: 9640622
    Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Niti Goel, Gilbert Dewey, Niloy Mukherjee, Matthew V. Metz, Marko Radosavljevic, Benjamin Chu-Kung, Jack T. Kavalieros, Robert S. Chau
  • III-N devices in Si trenches
    Patent number: 9640422
    Abstract: A trench comprising a portion of a substrate is formed. A nucleation layer is deposited on the portion of the substrate within the trench. A III-N material layer is deposited on the nucleation layer. The III-N material layer is laterally grown over the trench. A device layer is deposited on the laterally grown III-N material layer. A low defect density region is obtained on the laterally grown material and is used for electronic device fabrication of III-N materials on Si substrates.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Sanaz K. Gardner, Seung Hoon Sung, Marko Radosavljevic, Benjamin Chu-Kung, Sherry R. Taft, Ravi Pillarisetty, Robert S. Chau
  • HIGHLY POROUS FIBROUS NETWORK MATERIALS FOR GAS FILTRATION
    Publication number: 20170106334
    Abstract: Membranes are provided for filtering a gas, in some cases air. Membranes using a highly porous cellulose nano fibrous barrier layer with a highly porous (surface-charged) substrate can exhibit high flux, high retention, and low pressure drop in air filtration of toxic aromatic gases, fumes, bacteria, viruses, dusts, and particulate matters.
    Type: Application
    Filed: May 27, 2015
    Publication date: April 20, 2017
    Inventors: Benjamin Chu, Benjamin S. Hsiao, Hongyang Ma
  • III-N MATERIAL STRUCTURE FOR GATE-RECESSED TRANSISTORS
    Publication number: 20170104094
    Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.
    Type: Application
    Filed: December 22, 2016
    Publication date: April 13, 2017
    Inventors: Han Wui Then, Marko Radosavljevic, Uday Shah, Niloy Mukherjee, Ravi Pillarisetty, Benjamin Chu-Kung, Jack T. Kavalieros, Robert S. Chau
  • Strain compensation in transistors
    Patent number: 9614093
    Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Van H. Le, Benjamin Chu-Kung, Harold Hal W. Kennel, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros
  • Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs
    Patent number: 9583602
    Abstract: Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: February 28, 2017
    Assignee: Intel Corporation
    Inventors: Roza Kotlyar, Stephen M. Cea, Gilbert Dewey, Benjamin Chu-Kung, Uygar E. Avci, Rafael Rios, Anurag Chaudhry, Thomas D. Linton, Jr., Ian A. Young, Kelin J. Kuhn
  • Making a defect free fin based device in lateral epitaxy overgrowth region
    Patent number: 9583396
    Abstract: Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystalline defects in the fins due to lattice mismatch in the layer interfaces.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: February 28, 2017
    Assignee: Intel Corporation
    Inventors: Niti Goel, Benjamin Chu-Kung, Sansaptak Dasgupta, Niloy Mukherjee, Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Robert S. Chau, Ravi Pillarisetty
  • Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation
    Patent number: 9570614
    Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: February 14, 2017
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Sansaptak Dasgupta, Niti Goel, Van H. Le, Marko Radosavljevic, Gilbert Dewey, Niloy Mukherjee, Matthew V. Metz, Willy Rachmady, Jack T. Kavalieros, Benjamin Chu-Kung, Harold W. Kennel, Stephen M. Cea, Robert S. Chau
  • III-N TRANSISTORS WITH ENHANCED BREAKDOWN VOLTAGE
    Publication number: 20170018640
    Abstract: Techniques related to III-N transistors having enhanced breakdown voltage, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a hardmask having an opening over a substrate, a source, a drain, and a channel between the source and drain, and a portion of the source or the drain disposed over the opening of the hardmask.
    Type: Application
    Filed: March 26, 2014
    Publication date: January 19, 2017
    Inventors: Han Wui Then, Benjamin Chu-Kung, Sansaptak Dasgupta, Robert S. Chau, Seung Hoon Sung, Ravi Pillarisetty, Marko Radosavljevic
  • GERMANIUM-BASED QUANTUM WELL DEVICES
    Publication number: 20170012116
    Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
    Type: Application
    Filed: September 20, 2016
    Publication date: January 12, 2017
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Been-Yih Jin, Benjamin Chu-Kung, Matthew V. Metz, Jack T. Kavalieros, Marko Radosavljevic, Roza Kotlyar, Willy Rachmady, Niloy Mukherjee, Gilbert Dewey, Robert S. Chau
  • ASPECT RATIO TRAPPING (ART) FOR FABRICATING VERTICAL SEMICONDUCTOR DEVICES
    Publication number: 20170012125
    Abstract: Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant. A first source/drain region is disposed on the uppermost surface of the substrate and has a second, different, lattice constant. A vertical channel region is disposed on the first source/drain region. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.
    Type: Application
    Filed: March 28, 2014
    Publication date: January 12, 2017
    Inventors: Van H. LE, Benjamin CHU-KUNG, Gilbert DEWEY, Jack T. KAVALIEROS, Ravi PILLARISETTY, Willy RACHMADY, Marko RADOSAVLJEVIC, Matthew V. METZ, Niloy MUKHERJEE, Robert S. CHAU
  • SELECTIVELY REGROWN TOP CONTACT FOR VERTICAL SEMICONDUCTOR DEVICES
    Publication number: 20170012126
    Abstract: Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain region is disposed on the vertical channel region and has a second width parallel with and substantially greater than the first width. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.
    Type: Application
    Filed: March 28, 2014
    Publication date: January 12, 2017
    Applicants: Intel Corporation, Intel Corporation
    Inventors: Benjamin CHU-KUNG, Gilbert DEWEY, Van H. LE, Jack T. KAVALIEROS, Marko RADOSAVLJEVIC, Ravi PILLARISETTY, Han Wui THEN, Niloy MUKHERJEE, Sansaptak DASGUPTA
  • III-N material structure for gate-recessed transistors
    Patent number: 9530878
    Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Uday Shah, Niloy Mukherjee, Ravi Pillarisetty, Benjamin Chu-Kung, Jack T. Kavalieros, Robert S. Chau
  • STRAIN COMPENSATION IN TRANSISTORS
    Publication number: 20160372607
    Abstract: An embodiment includes a device comprising: a first epitaxial layer, coupled to a substrate, having a first lattice constant; a second epitaxial layer, on the first layer, having a second lattice constant; a third epitaxial layer, contacting an upper surface of the second layer, having a third lattice constant unequal to the second lattice constant; and an epitaxial device layer, on the third layer, including a channel region; wherein (a) the first layer is relaxed and includes defects, (b) the second layer is compressive strained and the third layer is tensile strained, and (c) the first, second, third, and device layers are all included in a trench. Other embodiments are described herein.
    Type: Application
    Filed: March 28, 2014
    Publication date: December 22, 2016
    Inventors: VAN H. LE, BENJAMIN CHU-KUNG, JACK T. KAVALIEROS, RAVI PILLARISETTY, WILLY RACHMADY, HAROLD W. KENNEL
  • CONTACT TECHNIQUES AND CONFIGURATIONS FOR REDUCING PARASITIC RESISTANCE IN NANOWIRE TRANSISTORS
    Publication number: 20160372560
    Abstract: Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.
    Type: Application
    Filed: August 30, 2016
    Publication date: December 22, 2016
    Inventors: Ravi Pillarisetty, Benjamin Chu-Kung, Willy Rachmady, Van H. Le, Gilbert Dewey, Niloy Mukherjee, Matthew V. Metz, Han Wui Then, Marko Radosavljevic
  • SELECTIVE EPITAXIALLY GROWN III-V MATERIALS BASED DEVICES
    Publication number: 20160365416
    Abstract: An embodiment includes a III-V material based device, comprising: a first III-V material based buffer layer on a silicon substrate; a second III-V material based buffer layer on the first III-V material based buffer layer, the second III-V material including aluminum; and a III-V material based device channel layer on the second III-V material based buffer layer. Another embodiment includes the above subject matter and the first and second III-V material based buffer layers each have a lattice parameter equal to the III-V material based device channel layer. Other embodiments are included herein.
    Type: Application
    Filed: March 28, 2014
    Publication date: December 15, 2016
    Inventors: MATTHEW V. METZ, JACK T. KAVALIEROS, GILBERT DEWEY, WILLY RACHMADY, BENJAMIN CHU-KUNG, MARKO RADOSAVLJEVIC, HAN WUI THEN, RAVI PILLARISETTY, ROBERT S. CHAU