Abstract: A method may include transmitting first test signals to electrical pathways of a connector-cable interface between a cable and a test circuit board in the absence of and in the presence of mechanical stress applied by a mechanical stressor to the connector-cable interface, performing vector network analysis measurements for one or more electrical parameters based on resultant signals from the electrical pathways resulting from the test signals in the absence of and in the presence of mechanical stress applied by the mechanical stressor to the connector-cable interface, transmitting one or more second test signals to electrical pathways of the connector-cable interface in the presence of mechanical stress applied by the mechanical stressor to the connector-cable interface, and based on differences between the vector network analysis measurements, determining whether or not the connector-cable interface has satisfied signal integrity requirements.

Abstract: A method may include transmitting one or more first test signals to electrical pathways of a connector-cable interface between a cable and a test circuit board in the absence of mechanical stress applied by a mechanical stressor to the connector-cable interface, performing measurements for one or more signal equalization parameters based on resultant signals from the electrical pathways resulting from the one or more first test signals in the 10 absence of and in the presence of mechanical stress applied by the mechanical stressor to the connector-cable interface, and based on differences between the measurements, determining whether or not the connector-cable interface has satisfied signal integrity requirements.

Abstract: A printed circuit board (PCB) includes first and second signal pads and a guard trace formed on a surface of the PCB. The first and second signal pads are for connecting to signal contacts of a high-speed data communication interface. The guard trace is located between the first signal pad and the second signal pad. The PCB further includes first, second, and third ground vias that couple the guard trace to a ground plane of the PCB. The first ground via is located at a first end of the guard trace. The second ground via is located at a second end of the guard trace. The third ground via is located between the first via and the second via.

Abstract: A printed circuit board substrate including multiple sets of glass rows. The multiple sets of glass rows include a first set of glass rows, a second set of glass rows, and a third set of glass rows. The first set of glass rows extend in a first direction. The second set of glass rows extend in a second direction that is perpendicular to the first direction. The third set of glass rows extend in a third direction that is parallel to the first direction. The resin holds the multiple sets of glass rows together and to fill pockets between the multiple of sets of glass rows.

Abstract: A circuit includes an inductive circuit trace and a nonlinear device. The circuit conducts a signal input to a load. The circuit trace receives the signal input at a first end of the circuit trace and provides the signal input to the load at a second end of the circuit trace. The nonlinear device is coupled at the second end and is configured to increase a voltage rise time of the signal input.

Abstract: A receiver includes an ODT network and a signal eye sampler. The ODT network terminates a data communication interface at a selectable impedance including a nominal impedance, at least one higher impedance, and at least one lower impedance. The signal eye sampler determines an eye margin for data received on the data communication interface. The receiver selects the nominal impedance, determines a nominal eye margin associated with the nominal impedance, selects a delta impedance from one of the higher impedance and the lower impedance, determines a delta eye margin associated with the delta impedance, determines whether the delta eye margin is greater than the nominal eye margin, and sets a run time impedance value for the data communication interface to the delta impedance when the delta eye margin is greater than the nominal eye margin.

Abstract: A printed circuit board comprising a differential microstrip pair including a neck-down area and an ultraviolet glue coating a portion of the neck-down area of the differential microstrip pair to control an impedance of the differential microstrip pair.

Abstract: An information handling system includes a baseboard management controller (BMC), an I/O device, and a BIOS. The BIOS initializes a parameter of the I/O device with a particular value, and includes an I/O health check module. Each time the BIOS initializes the first parameter, the I/O health check module receives the particular value, determines whether or not the particular value is within a predetermined range of values, and provides the particular value to the BMC. The BMC logs the values from each time the BIOS initializes the parameter, determines a health status for the information handling system based upon the logged values, and provides an indication of the health status.

Abstract: An add-in card includes a card-edge connector including a signal contact finger and a ground contact finger coupled to a ground plane of the add-in card, a plurality of metal layers, and first and second ground vias. The metal layers include a surface metal layer, a first ground metal layer, and a second ground metal layer. The surface metal layer includes the signal contact finger and the ground contact finger. The first ground metal layer is a closest metal layer to the surface metal layer, and the second ground metal layer is farther from the surface metal layer than the first ground metal layer. The first ground via is coupled to a first end of the ground contact finger, the first ground metal layer, and the second ground metal layer. The second ground via is coupled to a second end of the ground contact finger and the second ground metal layer, but is not coupled to the first ground metal layer.

Abstract: A printed circuit board includes a dielectric and a connector. The dielectric has a first dielectric constant. A first area within the dielectric has a second dielectric constant. The connector is mounted on the dielectric. The connector includes a first connector lead mounted on the dielectric, a first contact point above the dielectric, and a first connector wipe. The first connector wipe is disposed above the first area.

Abstract: A printed circuit board includes a dielectric and a connector. The connector is mounted on the dielectric. The connector includes a first connector lead, a first contact point, and a first connector wipe. The first connector wipe includes a first wider section adjacent to the first contact point. The first wider section creates an impedance mismatch between the first connector lead and the first connector wipe.

Abstract: A printed circuit board includes a dielectric and a connector. The connector is mounted on the dielectric. The connector includes a first connector lead, a first contact point, and a first connector wipe. The first connector wipe includes a plurality of low impedance bumps. The low impedance bumps create an impedance mismatch between the first connector lead and the first connector wipe.

Abstract: A printed circuit board includes a dielectric material, a signal trace on a surface of the dielectric material, a signal layer within the dielectric material, a via including plating, and multiple back drill locations. The plating provides an electrical communication between the signal trace and the signal layer, and the via has a diameter. The back drill locations are along a length of the via beyond the signal layer. A first combined diameter of the back drill locations at a bottom of the back drill locations is equal to the dimeter of the via. A second combined diameter of the back drill locations at a top of the back drill locations is greater than the dimeter of the via.

Abstract: A CPU includes a processor die and a substrate. The processor die includes first signal contacts, power contacts, and ground contacts. The processor die is affixed and electrically coupled to the substrate on a first surface of the substrate. The substrate routes the first signal contacts to associated second signal contacts on a second surface of the substrate. The substrate further routes a subset of the power contacts to a power pad on the first surface of the substrate, and routes a subset of the ground contacts to a ground pad on the first surface of the substrate.

Abstract: An information handling system includes a printed circuit board. The printed circuit board includes first and second pads of a first differential pair, a hatched ground, and first and second traces of a second differential pair. The first and second pads of the first differential pair are routed a surface of the printed circuit board. The hatched ground routed within a first layer of the printed circuit board. The first and second traces of the second differential pair are routed below the first and second pads and the hatched ground within a second layer of the printed circuit board. The hatched ground dampens crosstalk between signals on the traces and signals on the differential pair pads.

Abstract: A printed circuit board comprising a primary dielectric layer disposed underneath a microstrip trace and a secondary dielectric layer disposed above portions of the primary dielectric layer and the microstrip trace. The printed circuit board also includes a conductive plane disposed above the secondary dielectric layer and the microstrip trace, wherein the conductive plane is grounded.

Abstract: A printed circuit board comprising a first connection pad coupled to a first portion of a microstrip trace and a second connection pad coupled to a second portion of the microstrip trace. The microstrip trace has a first impedance along the first portion and a second impedance along the second portion. The printed circuit board also includes a conductive plane on a top surface of the microstrip trace, wherein the conductive plane includes a plurality of cutouts to reduce impedance mismatch between the first impedance and the second impedance.

Abstract: An information handling system includes a PCB, a transmitter for a data communication interface, a receiver for the data communication interface, a first channel instantiated in the printed circuit board, and a second channel instantiated in the printed circuit board. The receiver includes a first input and a second input. The first channel is coupled between an output of the transmitter and the first input of the receiver and is routed in a first path in the printed circuit board. The second channel is coupled to provide a reference voltage to the second input of the receiver and is routed in a second path in the printed circuit board. At least a portion of the second path is routed adjacent to a portion of the first path.

Abstract: A test system is provided for determining that data channels on a printed circuit board (PCB) have a predetermined impedance level. Each channel in the PCB is terminated at the predetermined impedance level. The PCB has a receptacle for coupling a device to the channels. An instrument can be installed into the receptacle, and includes connections to each of the channels, and a connector that is coupled to the connections by a channel splitter network. A test device is coupled to the connector and provides a test signal to the connector, receives a return signal from the connector, and determines that at least one of the channels does not have the predetermined impedance based upon the return signal.

Abstract: An integrated circuit device includes a multiplexor and multiple receivers for high-speed data communication interfaces. The multiplexor includes multiple signal inputs, a selector input, and a signal output. Each receiver includes a differential data signal input including a positive signal input and a negative signal input, a first termination resistor to terminate the positive signal input to a reference voltage node, a second termination resistor to terminate the negative signal input to the reference voltage node, and a noise measurement node to detect common mode noise at the reference voltage node, the noise measurement node coupled to an associated one of the signal inputs.