Abstract: An information handling system includes a PCB, a CPU, a power distribution hat, and a heat sink. The PCB includes a first power contact on a first surface of the PCB and a first ground contact on a second surface of the PCB. The CPU includes a substrate and is affixed and electrically coupled to the first surface of the PCB by a first surface of the substrate. A second surface of the substrate includes a second power contact and a second ground contact. The power distribution hat couples the first power contact with the second power contact. The heat sink couples the first ground contact with the second ground contact.

Abstract: A computing cable comprising a trace having a first impedance and an attenuator that includes a fixed resistor having a second resistance, a variable resistor having a first resistance, and a conductor having a second impedance. The combination of the first resistance, the second resistance, and the second impedance is based on the first impedance, wherein the first resistance is varied dynamically at runtime based on a control input.

Abstract: A printed circuit board (PCB) includes an array of signal pads on a first surface of the PCB, a power contact pad on the first surface, and a ground contact pad on a second surface of the PCB. Each signal pad of the array of signal pads is associated with a signal contact of a central processing unit (CPU). The power contact pad provides power for the CPU apart from the array of signal pads. The ground contact pad provides a ground for the CPU apart from the array of signal pads.

Abstract: A clock circuit is provided for clocking a high-speed data communication interface. The interface has (N) lanes. The clock circuit includes a triangle wave generator, N clock generators, and N lane FIFOs. The triangle wave generator provides P phase outputs, wherein P is greater than or equal to N. Each clock generator receives an associated one of the phase outputs and generates a clock signal having a frequency based upon the phase output. Each FIFO receives data and an associated one of the clock signals, and provides the data at a clock frequency associated with the associated clock signal.

Abstract: A printed circuit board includes first and second insulating layers, first and second strip line circuit traces formed on a surface of the first insulating layer, and a patterned dielectric material. The first strip line circuit trace has a first length and carries a first signal. The second strip line circuit trace is adjacent to the first strip line circuit trace, has a second length longer than the first length, and carries a second signal. The patterned dielectric material is provided over a portion of the first length to delay the first signal relative to the second signal. The second insulating layer is affixed to the surface and covers the first and second strip line circuit traces and the patterned dielectric material.

Abstract: A printed circuit board includes a first and second microstrip circuit traces formed on an outer surface of the printed circuit board, and a patterned dielectric material applied over a first length of the first microstrip circuit trace. The first microstrip circuit trace has a first length and carries a first signal. The second microstrip circuit trace is adjacent to the first microstrip circuit trace, has a second length longer than the first length, and carries a second signal. The patterned dielectric material is provided over a portion of the first length to delay the first signal relative to the second signal.

Abstract: A printed circuit board includes metal layers, a metalized circuit via interconnecting a first one of the metal layers and a second one of the metal layers, and a back-drill hole drilled to remove metalization of the circuit via from a third metal layer adjacent to the second metal layer to a fourth metal layer at a first surface of the printed circuit board. The back-drill hole has a profile that includes a first undercut at a bottom of the first back-drill hole.

Abstract: An information handling system includes a memory subsystem and a basic/input out system (BIOS). The BIOS performs multiple trainings of the memory subsystem, and each of the trainings is performed at a different temperature. The BIOS stores multiple derating values in a derating table of the BIOS, and each of the derating values corresponds to a respective tap value at a respective temperature. During a subsequent power on self test of the information handling system, the BIOS performs a first training of the memory subsystem, and stores a first set of tap values. During a runtime of the information handling system, a memory controller determines whether a temperature of the information handling system has changed by a predetermined amount. In response to the temperature changing by the predetermined amount, the memory controller utilizes the derating values in the derating table to automatically update the tap values.

Abstract: An information handling system includes a PCB, a CPU, a power distribution hat, and a heat sink. The PCB includes a first power contact on a first surface of the PCB and a first ground contact on a second surface of the PCB. The CPU includes a substrate and is affixed and electrically coupled to the first surface of the PCB by a first surface of the substrate. A second surface of the substrate includes a second power contact and a second ground contact. The power distribution hat couples the first power contact with the second power contact. The heat sink couples the first ground contact with the second ground contact.

Abstract: A data communications cable may communicatively coupled two components associated with an information handling system. For example, the data communications cable may include: a differential pair of conductors; a first dielectric material, associated with a first relative permittivity, surrounding the differential pair of conductors; and a second dielectric material, associated with a second relative permittivity, surrounding the first dielectric material. For instance, the first relative permittivity may be greater than the second relative permittivity, and a distance between the differential pair of conductors may vary plus or minus an amount with a length of the data communications cable.

Abstract: A high-speed transmission circuit comprises, as part of a signal path, a connector pin disposed on a pad that comprises an unused pad region. The unused pad region is not considered part of the signal path but is part of a resonant sub-circuit. In various embodiments, by properly adjusting the dimensions of the pad region and other structures in the high-speed transmission circuit, resonant frequencies of the sub-circuit are shifted to a frequency range that is outside of the frequency range of interest in the signal path, thereby, reducing insertion loss and increasing signal integrity without compromising mechanical stability.

Abstract: An inhomogeneous dielectric medium high-speed signal trace system includes a first and second ground layer. A first dielectric layer is located adjacent the first ground layer. A second dielectric layer has a different dielectric constant and a greater thickness than the first dielectric layer, and is located between the first dielectric layer and the second ground layer. A first differential trace pair is located between the first dielectric layer and the second dielectric layer, and includes a trace spacing that is less than or equal to a thickness of the first dielectric layer. The first different trace pair transmit signals and, in response, produces a magnetic field, and the trace spacing prevents a magnetic field strength of the magnetic field from exceeding a magnetic field strength threshold at a second differential trace pair that is located adjacent the first differential trace pair.

Abstract: An information handling system includes a first component including a transmitter for a high-speed serial data interface, and a second component including a receiver for the high-speed serial data interface. The receiver includes an equalization stage and a decision feedback equalization (DFE) stage. The equalization stage has an input to configure the equalization stage in one of a first low equalization state and a first high equalization state. The DFE stage has a plurality of tap inputs. The first component provides a plurality of training runs on the high-speed serial data interface.

Abstract: An apparatus includes a first conductor trace arranged to electrically couple a first complementary signal to provide differential signaling. The first conductor trace includes a first plurality of split traces to conduct the first complementary signal, and a first plurality of tie bars to connect the first split traces.

Abstract: A flying probe includes a test module and a processor. The test module measures a plurality of delta capacitances associated with a plurality of vias in a printed circuit board. The plurality of vias include first, second, third and fourth vias. Each different delta capacitance is measured between a different pair of the vias. The processor compares all the delta capacitances to a threshold value. In response to multiple delta capacitances associated with the first via being greater than or equal to the threshold value, the processor detects a possible via stripping issue for the first via.

Abstract: A high-speed data communication interface includes first and second lanes. The first lane includes a first transmitter coupled to send a first data signal to a first receiver via a first channel. The second lane includes a second transmitter coupled to send a second data signal to a second receiver via a second channel. The first channel injects crosstalk into the second channel. The second transmitter sets a duty cycle adjuster input to adjust a duty cycle of the second data signal to reduce the crosstalk.

Abstract: A printed circuit board (PCB) includes a metal layer and a via. The via is coupled to a portion of the metal layer. The portion of the metal layer forms a flange of a beam structure in the PCB. The via forms a web of the beam structure in the PCB.

Abstract: An information handling system includes a printed circuit board. The printed circuit board includes first and second pads of a first differential pair, a hatched ground, and first and second traces of a second differential pair. The first and second pads of the first differential pair are routed a surface of the printed circuit board. The hatched ground routed within a first layer of the printed circuit board. The first and second traces of the second differential pair are routed below the first and second pads and the hatched ground within a second layer of the printed circuit board. The hatched ground dampens crosstalk between signals on the traces and signals on the differential pair pads.

Abstract: An information handling system includes a printed circuit board, which in turn includes a differential pair, a ground trace, and a ground via. The differential pair includes first and second traces. The ground trace is routed between the first and second traces of the differential pair. The ground via is located along the ground trace. The ground trace and the ground via combine to create a common mode signal filter, which in turn resets a skew of the differential pair.

Abstract: An information handling system includes a printed circuit board having a signal via fabricated through the printed circuit board. The signal via includes a conductive metal plating. The signal via also includes first and second via portions. The first via portion is connected to a first trace of a differential pair. The second via portion is connected to a second trace of the differential pair. The first and second via portions are formed in the conductive metal plating.