Abstract: A printed circuit board of an information handling system includes a pair of signal vias including a pair of keepout objects. Each one of the keepout objects surrounds one of the signal vias. The printed circuit board includes a pair of signal traces that includes a positive signal trace and a negative signal trace, wherein the pair of signal traces are between the keepout objects, and wherein a width of each of the signal traces is increased.

Abstract: A cable comprising a conductor in a center of the cable, a dielectric layer surrounding the conductor and a resistive coating may be provided. The resistive coating may be applied to an exposed portion of the conductor and disposed with the dielectric layer. The resistance of the resistive coating when combined with an impedance of the cable prior to application of the resistive coating reaches a target impedance.

Abstract: An information handling system includes a PCB, a CPU, a power distribution hat, and a heat sink. The PCB includes a first power contact on a first surface of the PCB and a first ground contact on a second surface of the PCB. The CPU includes a substrate and is affixed and electrically coupled to the first surface of the PCB by a first surface of the substrate. A second surface of the substrate includes a second power contact and a second ground contact. The power distribution hat couples the first power contact with the second power contact. The heat sink couples the first ground contact with the second ground contact.

Abstract: A connector includes a connector core and ant outer shell. The connector core includes a plurality of contacts for coupling a device to a PCB, The connector core exhibits a first impedance for signals provided on the contacts. The outer shell is configured to be rigidly attached to the connector core. When the outer shell has a first configuration and is attached to the connector core, the connector exhibits a second impedance for signals provided on the contacts, the second impedance being different from the first impedance. When the outer shell has a second configuration and is attached to the connector core, the connector exhibits a third impedance for signals provided on the contacts, the third impedance being different from the first and second impedances.

Abstract: A CPU includes a processor die and a substrate. The processor die includes first signal contacts, power contacts, and ground contacts. The processor die is affixed and electrically coupled to the substrate on a first surface of the substrate. The substrate routes the first signal contacts to associated second signal contacts on a second surface of the substrate. The substrate further routes a subset of the power contacts to a power pad on the first surface of the substrate, and routes a subset of the ground contacts to a ground pad on the first surface of the substrate.

Abstract: A clock circuit is provided for clocking a high-speed data communication interface. The interface has (N) lanes. The clock circuit includes a triangle wave generator, N clock generators, and N lane FIFOs. The triangle wave generator provides P phase outputs, wherein P is greater than or equal to N. Each clock generator receives an associated one of the phase outputs and generates a clock signal having a frequency based upon the phase output. Each FIFO receives data and an associated one of the clock signals, and provides the data at a clock frequency associated with the associated clock signal.

Abstract: A printed circuit board (PCB) includes an array of signal pads on a first surface of the PCB, a power contact pad on the first surface, and a ground contact pad on a second surface of the PCB. Each signal pad of the array of signal pads is associated with a signal contact of a central processing unit (CPU). The power contact pad provides power for the CPU apart from the array of signal pads. The ground contact pad provides a ground for the CPU apart from the array of signal pads.

Abstract: An information handling system includes a memory device and a processor. The memory device includes first data representing a thermal profile of a motherboard, and second data representing a circuit trace of the motherboard. The circuit trace provides a high-speed data interconnection between two or more circuit devices. The processor determines an average temperature of the circuit trace on the motherboard based upon the first data and the second data, and models a trace layout for the circuit trace on the motherboard based upon the average temperature.

Abstract: An information handling system includes a first component including a transmitter for a high-speed serial data interface, and a second component including a receiver for the high-speed serial data interface. The receiver includes an equalization stage and a decision feedback equalization (DFE) stage. The equalization stage has an input to configure the equalization stage in one of a first low equalization state and a first high equalization state. The DFE stage has a plurality of tap inputs. The first component provides a plurality of training runs on the high-speed serial data interface.

Abstract: A contact for a high-speed data communication interface includes a first portion configured to be coupled to a first component associated with the high-speed data communication interface, a second portion configured to be coupled to a mating contact of a second component associated with the high-speed data communication interface, and a third portion configured to provide a sliding surface when coupled to the mating contact. The sliding surface is coated with a ferromagnetic coating.

Abstract: A paddle card includes a printed circuit board and a twin-axial cable. The PCB includes a first signal pad on a top surface of the PCB and a second signal pad on a bottom surface of the PCB. The second signal pad is directly below the first signal pad. The twin-axial cable includes a first signal conductor coupled to the first signal pad and a second signal conductor coupled to the second signal pad.

Abstract: An information handling system includes a high-speed data communication link and a processor. The link includes lanes that each includes a transmitter with an equalization setting and a receiver. The processor initiates a training of the high-speed data communication interface to determine a setting value for the equalization setting for each lane, determines a lane quality value for each lane based upon the associated setting value, determines a link score based on the lane quality values, and determines that the lane quality score is outside a threshold range. In response to determining that the lane quality score is outside the threshold range, the processor selects a lane that has a lane quality value that has a greater magnitude than the lane quality values of all other lanes, increases the equalization setting of the first lane, and initiates a retraining of the other lanes.

Abstract: An inhomogeneous dielectric medium high-speed signal trace system includes a first and second ground layer. A first dielectric layer is located adjacent the first ground layer. A second dielectric layer has a different dielectric constant and a greater thickness than the first dielectric layer, and is located between the first dielectric layer and the second ground layer. A first differential trace pair is located between the first dielectric layer and the second dielectric layer, and includes a trace spacing that is less than or equal to a thickness of the first dielectric layer. The first different trace pair transmit signals and, in response, produces a magnetic field, and the trace spacing prevents a magnetic field strength of the magnetic field from exceeding a magnetic field strength threshold at a second differential trace pair that is located adjacent the first differential trace pair.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may measure at least one of a first height value and a first width value of a first eye diagram of a first signal; measure at least one of a second height value and a second width value of a second eye diagram of a second signal; determine at least one of a height difference value and a width difference value respectively between the at least one of the first height value and the first width value of the first eye diagram and the at least one of the second height value and the second width value of the second eye diagram; and determine that the at least one of the height difference value and the width difference value respectively meets or exceeds a height threshold value or a width threshold value.

Abstract: A printed circuit board (PCB) is provided for transmitting a differential signal. The PCB includes first and second conductive signal layers. The first conductive signal layer includes a first positive trace of the differential signal and a first negative trace of the differential signal. The second conductive signal layer includes a second positive trace of the differential signal and a second negative trace of the differential signal. The first positive trace is adjacent to the first negative trace, and the second positive trace is adjacent to the second negative trace and directly below the first negative trace.

Abstract: An information handling system includes a dual in-line memory module (DIMM) and a memory controller coupled to the DIMM via a data bus. The memory controller determines that a first lane of a byte group of the data bus is more susceptible to crosstalk than a second lane of the byte group, determines a first performance level of the first lane, changes a delay (D) of a third lane of the byte group, the third lane being adjacent to the first lane, and determines that a second performance level of the first lane is different from the first performance level in response to delaying the third lane.

Abstract: A data communications cable may communicatively coupled two components associated with an information handling system. For example, the data communications cable may include: a differential pair of conductors; a first dielectric material, associated with a first relative permittivity, surrounding the differential pair of conductors; and a second dielectric material, associated with a second relative permittivity, surrounding the first dielectric material. For instance, the first relative permittivity may be greater than the second relative permittivity, and a distance between the differential pair of conductors may vary plus or minus an amount with a length of the data communications cable.

Abstract: An add-in card printed circuit board (PCB) includes a body portion and a card edge portion. The body portion includes a circuit trace associated with a high-speed data communication interface. The card edge portion includes contact fingers, and is configured to be inserted into a card edge connector of an information handling system. The contact fingers include a signal contact finger coupled to the circuit trace, and a ground contact finger that is located adjacent to the signal contact finger. The ground contact finger includes a ground via that couples the ground contact finger to a ground plane layer of the add-in card PCB. The ground via is located half way within the body portion and half way within the card edge portion.

Abstract: An information handing system includes a transmitter, a receiver, and a differential signal channel. The transmitter provides a differential signal on a pair of differential outputs. The receiver receives the differential signal on a pair of differential inputs. The differential signal channel carries the differential signal from the differential outputs to the differential inputs. The differential signal is provided on the differential signal channel as a voltage swing between a first positive voltage and a first negative voltage with reference to a ground plane of the information handling system.

Abstract: A system for providing signal temperature immunity to a printed circuit board (PCB) comprises moating a set of reference planes, forming a trench between a heat source and a stripline trace and positioning a perforated section of a plane on a reference plane opposite the heat source. Moating the reference planes increases thermal resistance, the trench removes dielectric material and replaces it with air and the perforated section causes heat to travel in a non-linear path. Vias positioned at the ends of the PCB route heat along the outer surfaces of the PCB to transfer heat to the ambient environment.