Abstract: Systems and methods are provided that may be implemented in-situ and on-chip to capture a digital signal eye of a serial transmit signal produced by a transmitter circuit of integrated SerDes PHY transceiver circuitry. In one example, a serial transmit signal produced by a transmitter side circuit of an integrated SerDes PHY transceiver circuit may be looped back on chip to the receiver side circuit of the same SerDes PHY transceiver circuit such that an integrated digital eye monitor circuit of the SerDes receiver circuit may capture the digital eye of the serial transmit signal of the same SerDes PHY circuit. In another example, a digital eye monitor circuit may be integrated on the transmitter side of an integrated SerDes PHY transceiver circuit such that a serial transmit signal produced by the transmitter side circuit of may be captured on-chip.

Abstract: Methods and mechanisms for mitigating attenuation in a printed circuit board connection may include selecting the relative permittivities of resin layers proximate to the connection to control connection frequency resonances such that the attenuation of signals in the connection due to frequency resonance is mitigated.

Abstract: An electrical connector may be used to connect and propagate signals between electrical systems, devices, and components. The electrical connector may comprise a male conductor component with one or more contacts positioned on a member. The electrical connector may comprise a female conductor component configured to be a receptacle for receiving a portion of the male conductor and having one or more moveable conduction arms which may be actuated to contact respective one or more contacts positioned on the member of the male conductor component.

Abstract: A circuit board includes a board base with a first surface and a second surface that is located opposite the first surface. A plurality of first coupling pads are located on the first surface of the board base. A plurality of second coupling pads are located on the second surface of the board base. The first coupling pads and the second coupling pads define a coupling pad footprint. A breakout via system is included in the board base. The breakout via system includes a plurality of primary signal vias that are located in the board base and outside of the coupling pad footprint, a plurality of first primary signal via connections that extend between the primary signal vias and the plurality of first coupling pads, and a plurality of second primary signal via connections that extend between the primary signal vias and the plurality of second coupling pads.

Abstract: A board adapter system includes a first adapter board. A secondary first processor coupling is located on the first adapter board, and the first adapter board passes signals between a primary first processor coupling on a first board and a first processor coupled to the secondary first processor coupling when the first adapter board engages the primary first processor coupling. A first/third processor communication bus extends between the secondary first processor coupling and the second board connector on the first adapter board, and passes signals between the first processor and a third processor that is coupled to the second board connector. A first/fourth processor communication bus extends between the secondary first processor coupling and the second board connector, and passes signals between the first processor and a fourth processor that is coupled to the second board connector on the first adapter board.

Abstract: The time domain response of a simulated system is simulated by first receiving variables for the simulated system. A frequency domain simulation is performed over different frequencies using each of the variables to provide simulated frequency domain responses for the simulated system. A time domain simulation is performed over the different frequencies using a subset of simulated frequency domain responses to produce a plurality of simulated time domain responses for the simulated system. The subset of the simulated frequency domain responses is mapped to the plurality of simulated time domain responses to produce a frequency-domain-to-time-domain mapping. A plurality of mapped time domain responses is determined using the frequency-domain-to-time-domain mapping, where the plurality of simulated time domain responses and the plurality of mapped time domain responses provide time domain responses for each of the plurality of variables for the simulated system.

Abstract: A receiver circuit detects an eye margin within a differential signal having a true component and a complement component. A transmitter circuit adjusts a phase between the true component and the complement component of the differential signal, based on the eye margin, to improve the eye margin. Improving the eye margin results from a reduction in common mode noise within the differential signal.

Abstract: A method, system, and computer program product for exploring and optimizing an electrical design space. A computer receiving a design space assigns a plurality of initial values (random or predetermined) for optimizing the design space. A particle swarm containing a plurality of particles is created and an optimization of the design space is then performed using the assigned initial values. Following completion of optimization, the global best and personal best for each particle are updated. Velocity vectors and position vectors of the design space are then updated before the computer performs the optimization process again. The process loops, continually updating global and personal bests and velocity and position vectors until a termination criteria is reached. Upon reaching the termination criteria, the best fitness of each particle of the swarm is assigned as an optimized design space. In an alternate embodiment, the particle with the worst target fitness may be assigned.

Abstract: A receiver circuit detects an eye margin within a differential signal having a true component and a complement component. A transmitter circuit adjusts a phase between the true component and the complement component of the differential signal, based on the eye margin, to improve the eye margin.

Abstract: One embodiment of the invention provides a multi-layered ceramic package. The ceramic package includes a signal layer having a plurality of signal lines and a mesh reference layer parallel to the signal layer. The mesh reference layer includes a plurality of intersecting reference lines of varying reference-line width in the plane of the mesh layer. The mesh reference lines may be widened in locations of probable signal cross-talk. Other embodiments of the invention include software for optimizing a ceramic package design by selectively widening mesh lines in regions of probable cross-talk, and systems for designing and manufacturing such a ceramic package.

Abstract: A method, system, and computer program product for exploring and optimizing an electrical design space. A computer receiving a design space assigns a plurality of initial values (random or predetermined) for optimizing the design space. A particle swarm containing a plurality of particles is created and an optimization of the design space is then performed using the assigned initial values. Following completion of optimization, the global best and personal best for each particle are updated. Velocity vectors and position vectors of the design space are then updated before the computer performs the optimization process again. The process loops, continually updating global and personal bests and velocity and position vectors until a termination criteria is reached. Upon reaching the termination criteria, the best fitness of each particle of the swarm is assigned as an optimized design space. In an alternate embodiment, the particle with the worst target fitness may be assigned.

Abstract: A signal history controlled slew-rate transmission method and bus interface transmitter provide an improved channel equalization mechanism having low complexity. A variable slew-rate feed-forward pre-emphasis circuit changes the slew rate of the applied pre-emphasis in conformity with the history of the transmitted signal. The pre-emphasis circuit may be implemented by a pair of current sources supplying the output of the transmitter, and having differing current values. The current sources are controlled such that upon a signal value change, a high slew rate is provided and when the signal value does not change for two consecutive signal periods, the slew rate is reduced. A current source having a controlled magnitude may be employed to provide a slew rate that changes over time and is continuously reduced until another transmission value change occurs.