Abstract: The present invention relates to an inert carrier Salmonella and potential use thereof, which is expected to be developed into a new inert carrier bacteria, and can be applied to the development of an indirect agglutination test method for simple and rapid detection of antigens or infected antibodies. The inert carrier Salmonella has been deposited in CGMCC in Beijing on Mar. 18, 2019 with the accession number of CGMCC No. 17340, and is classified as Salmonella sp. with a strain code of S9. The Salmonella has no visible agglutination reaction with various chicken sera derived from different genetic backgrounds, i.e., it has no non-specific agglutination reaction with chicken sera derived from broad range of genetic backgrounds.

Abstract: The present invention belongs to the technical field of multiple bolt transverse load loosing testers, and relates to a closed loop control method for transverse load amplitude of multiple bolt loosing tester. The closed loop control method is used to conduct stepless amplitude modulation and accurate control for transverse loads of a multiple bolt loosing tester, thereby realizing stepless amplitude modulation and accurate control for the transverse loads. The closed loop control method is realized based on the multiple bolt loosing tester. The multiple bolt loosing tester consists of four parts: a transverse load amplitude control part, a transverse load transmission part, a torque load transmission part and an axial load transmission part. The present invention can provide stepless amplitude modulation continuous transverse loads for a flange bolt set and guarantee the accuracy of the transverse loads through a closed loop control system.

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with a heterojunction bipolar transistor (HBT) integrated with a gate-all-around (GAA) transistor. One example semiconductor device generally includes a first substrate, a second substrate adjacent to the first substrate, a GAA transistor disposed above the first substrate, and a HBT disposed above the second substrate. Other aspects of the present disclosure generally relate to a method for fabricating a semiconductor device. An exemplary fabrication method generally comprises forming a GAA transistor disposed above a first substrate and forming a HBT disposed above a second substrate, wherein the second substrate is adjacent to the first substrate.

Abstract: A connector is disclosed. In an embodiment, the connector includes a first connection part and a second connection part. The first connection part and the second connection part form a groove suitable for accommodating a circuit board when the first connection part and the second connection part are assembled together, and elastic parts are disposed on opposite inner surfaces of the groove. Furthermore, a corresponding three-way transmission and conversion circuit module is disclosed, including the connector.

Abstract: Provided is a user side load response method based on adjustment and control on temperature of load clusters. The user side load response method includes: performing thermodynamic modeling on a temperature control load to obtain a temperature control model in direct load control; constructing a mapping quantity to describe the change state of a temperature control load relay switch; obtaining adjustable capacity of the temperature control load through the mapping quantity; introducing temperature control load clusters to solve the problem that control precision cannot satisfy condition requirements; and finally calculating the influence of each load cluster in different load cluster control schemes on comfort degree.

Abstract: Certain aspects of the present disclosure generally relate to a vertically stacked multilayer resistive random access memory (RRAM) and methods for fabricating such an RRAM. The vertically stacked multilayer RRAM generally includes a planar substrate layer and a plurality of metal-insulator-metal (MIM) stacks, each MIM stack structure of the plurality of MIM stacks comprising a plurality of MIM structures extending orthogonally above the planar substrate.

Abstract: A gate-all-around (GAA) transistor has an insulator on a substrate. The GAA transistor also may have different crystalline structures for P-type work material and N-type work material. The GAA transistor includes one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire, nanosheet, or nanoslab semiconductors, are surrounded along a longitudinal axis by gate material. At a first end of the channel is a source region and at an opposite end of the channel is a drain region. To reduce parasitic capacitance between a bottom gate section and a substrate, an insulator is added on the substrate. Further improvements are made in performance of a circuit having both P-type work material and N-type work material by providing different crystalline lattice structures for the work material.

Abstract: Method, systems and apparatuses may provide for technology that divides an application into a plurality of portions that are each associated with one or more functions of the application and determine a plurality of transition probabilities between the plurality of portions. Some technology may also receive at least a first portion of the plurality of portions, and receive a relation file indicating the plurality of transition probabilities between the plurality of portions.

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device having an insulator region disposed on at least one edge of a semiconductor fin structure. An example semiconductor device generally includes a first semiconductor region, an insulator region, a double diffusion break, and a first gate region. The first semiconductor region comprises a first fin structure and a second fin structure separated by a cavity. The insulator region is disposed along an edge of the first fin structure. The double diffusion break is disposed adjacent to the insulator region in the cavity. The first gate region is disposed around a portion of the first fin structure.

Abstract: A disclosed multimode optical fiber comprises a core and a cladding surrounding the core. The core has an outer radius r1 in between 20 ?m and 30 ?m. The cladding includes a first outer cladding region having an outer radius r4a and a second outer cladding region having an outer radius r4b less than or equal to 45 ?m. The second outer cladding region comprises silica-based glass doped with titania. The optical fiber further includes a primary coating with an outer radius r5 less than or equal to 80 ?m, and a thickness (r5?r4) less than or equal to 30 ?m. The optical fiber further includes a secondary coating with an outer radius r6 less than or equal to 100 ?m. The secondary coating has a thickness (r6?r5) less than or equal to 30 ?m, and a normalized puncture load greater than 3.6×10?3 g/micron2.

Abstract: The optical fibers disclosed is a single mode optical fiber comprising a core region and a cladding region surrounding and directly adjacent to the core region. The core region can have a radius r1 in a range from 3 ?m to 7 ?m and a relative refractive index profile ?1 having a maximum relative refractive index ?1max in the range from 0.25% to 0.50%. The cladding region can include a first outer cladding region and a second outer cladding region surrounding and directly adjacent to the first outer cladding region. The first outer cladding region can have a radius r4a. The second outer cladding region can have a radius rob less than or equal to 45 ?m and comprising silica based glass doped with titania.

Abstract: Disclosed a leaf positioning device (100) for a multi-leaf collimator, comprising: a plurality of positioning signal transmitters which are in the leaf guide rail box, wherein the plurality of positioning signal transmitters are arranged opposite to a first end surface of leaves of the multi-leaf collimator; a plurality of positioning signal receivers which are in the leaf guide rail box and corresponding to the plurality of positioning signal transmitters, wherein the plurality of positioning signal receivers are arranged opposite to a second end surface of the leaves of the multi-leaf collimator; wherein, the plurality of positioning signal transmitters are configured to transmit positioning signals to the plurality of positioning signal receivers, and the plurality of positioning signal receivers are configured to generate output signals according to the positioning signals; a positioning device which is connected to each of the plurality of positioning signal receivers, wherein the positioning device is c

Abstract: Examples herein include thermally conductive pathways for glass substrates such as used by passive on glass devices that may be used to enhance the thermal conductivity of an integrated POG device. By using a thermally conductive material for passivation of the device pathways during manufacturing, the device pathways may be able to conduct heat away from the device. For example, by using a selected poly (p-phenylene benzobisoxazole) (PBO) based material (e.g., poly-p-phenylene-2, 6-benzobisoxazole) instead of conventional polyimide (PI) materials during a Cu pattern passivation process, the overall thermal performance of the device, may be enhanced.

Abstract: Before a semiconductor die of a brittle compound semiconductor is encapsulated with a molding compound during package fabrication, side surfaces of the semiconductor die are treated to avoid or prevent surface imperfections from propagating and fracturing the crystal structure of the substrate of the III-V compound semiconductor under the stresses applied as the molding compound solidifies. Surfaces are treated to form a passivation layer, which may be a passivated layer of the substrate or a passivation material on the substrate. In a passivated layer, imperfections of an external layer are transformed to be less susceptible to fracture. Passivation material, such as a poly-crystalline layer on the substrate surface, diffuses stresses that are applied by the molding compound. Semiconductor dies in flip-chip and wire-bond chip packages with treated side surfaces as disclosed have a reduced incidence of failure caused by die fracturing.

Abstract: The present disclosure provides a method for displaying a three-dimensional space view. The three-dimensional space view includes a first three-dimensional space view and a second three-dimensional space view. The method includes presenting the first three-dimensional space view on a first user interface; presenting the second three-dimensional space view on a second user interface; changing the first three-dimensional space view according to a user input; and changing the second three-dimensional space view according to a change in the first three-dimensional space view.

Abstract: The present disclosure provides a method for displaying a three-dimensional space view. The three-dimensional space view includes a first three-dimensional space view and a second three-dimensional space view. The method includes presenting the first three-dimensional space view on a first user interface; presenting the second three-dimensional space view on a second user interface; changing the first three-dimensional space view according to a user input; and changing the second three-dimensional space view according to a change in the first three-dimensional space view.

Abstract: The present disclosure provides systems and methods that apply neural networks such as, for example, convolutional neural networks, to sparse imagery in an improved manner. For example, the systems and methods of the present disclosure can be included in or otherwise leveraged by an autonomous vehicle. In one example, a computing system can extract one or more relevant portions from imagery, where the relevant portions are less than an entirety of the imagery. The computing system can provide the relevant portions of the imagery to a machine-learned convolutional neural network and receive at least one prediction from the machine-learned convolutional neural network based at least in part on the one or more relevant portions of the imagery. Thus, the computing system can skip performing convolutions over regions of the imagery where the imagery is sparse and/or regions of the imagery that are not relevant to the prediction being sought.

Abstract: Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a ferroelectric (FE) semiconductor device having a channel region; a gate oxide; a FE region, wherein the gate oxide is disposed between the FE region and the channel region; a gate region, wherein the FE region is disposed between the gate oxide and the gate region; a first semiconductor region disposed adjacent to the channel region; and a second semiconductor region disposed adjacent to the channel region. The semiconductor device may also include a transistor, wherein a region of the transistor is connected to the gate region, the first semiconductor region, or the second semiconductor region of the FE semiconductor device.

Abstract: A deep partial transfer method weighted by a domain asymmetry factor for rolling bearing fault diagnosis includes: first, extracting the deep transfer fault features from the monitoring data of the source rolling bearing and the target rolling bearing by a deep residual network; second, training the domain confusion network by using the deep transfer fault feature, and calculating the domain asymmetric factor; next, calculating the maximum mean discrepancy implanted by a multiple polynomial kernels of the fault features of the adaptation layer of the deep residual network, and using the domain asymmetry factor weighting to suppress the contribution of outlier fault features of the source rolling bearing; and finally, building the objective function using the weighted maximum mean discrepancy implanted by the multiple polynomial kernels to train the deep residual network.

Abstract: Examples herein include thermally conductive pathways for glass substrates such as used by passive on glass devices that may be used to enhance the thermal conductivity of an integrated POG device. By using a thermally conductive material for passivation of the device pathways during manufacturing, the device pathways may be able to conduct heat away from the device. For example, by using a selected poly (p-phenylene benzobisoxazole) (PBO) based material (e.g., poly-p-phenylene-2, 6-benzobisoxazole) instead of conventional polyimide (PI) materials during a Cu pattern passivation process, the overall thermal performance of the device, may be enhanced.