Abstract: Examples of the present disclosure provide a semiconductor device, a fabrication method thereof, and a memory system. The semiconductor device includes: a memory array in a first region of the semiconductor device; first semiconductor portions located in a second region of the semiconductor device and spaced apart from each other along a first direction; a conductive structure; and an isolation structure. The second region is different from the first region; the conductive structure is on a first side of the first semiconductor portions; and the isolation structure includes a first isolation portion in the second region, where the first isolation portion extends along the first direction or a second direction, the first isolation portion extends through at least one first semiconductor portion, and the second direction intersects with the first direction.

Abstract: A semiconductor device includes decks stacked over a semiconductor layer in a vertical direction. Each deck includes alternating word line layers and insulating layers. A gate line structure (GLS) extends through the word line layers and the insulating layers of the decks. A channel structure extends through the word line layers and the insulating layers of the decks. A sidewall of the GLS is discontinuous at a border between two neighboring decks, and a sidewall of the channel structure is discontinuous at an interface between two neighboring decks. The GLS includes a first GLS that includes a gate line slit, a second GLS that includes sub-GLSs spaced apart from each other in a horizontal direction, or a combination thereof.

Abstract: The present disclosure discloses a gate drive circuit and a display panel. The gate drive circuit includes a plurality of shift registers. Each shift register includes a level transmission signal selection module, a pull-up control module, a pulse quantity reduction module, a first inverting module, a first output module, a second output module, and a voltage boosting module. By connecting the voltage boosting module between a second electrode of a second transistor and a low potential line in series, when a first transistor is turned on, a potential of the second electrode of the second transistor can be increased, and on-state current of the second transistor can be reduced, so that a pulse amplitude of a second gate drive signal can be increased and stabilized.

Abstract: An implementation of a memory device includes a stack structure having alternating first layers and dielectric layers. The stack structure has a first surface and a second surface opposite to the first surface. First contact structures include a conductive material. The first contact structures penetrate from the first surface into the stack structure to be in contact respectively with a first portion of first layers. Second contact structures include a conductive material. Each of the second contact structures penetrates from the second surface into the stack structure to be in contact respectively with a remainder portion of conductive layers other than the first portion of the first layers.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers, a landing structure and a contact structure. The gate layers and the insulating layers are stacked alternatingly, and form stair steps in a staircase region. The landing structure is disposed on a first gate layer of a first stair step of the stair steps in the staircase region. The landing structure includes an upper structure and an isolation stack between the upper structure and the first gate layer. The upper structure is etch-selective to a contact isolation layer that covers the staircase region. The contact structure extends through the contact isolation layer and the landing structure and is connected with the first gate layer of the first stair step.

Abstract: The present disclosure relates methods, devices, systems, and techniques for merging schemes in semiconductor devices such as three-dimensional (3D) semiconductor devices. In one aspect, a semiconductor device includes a semiconductor structure that includes a stack of conductive layers and insulating layers alternating with each other along a first direction. The semiconductor structure includes an array region and a connection region adjacent to the array region in a second direction perpendicular to the first direction. The semiconductor device further includes multiple contact structures extending through the connection region along the first direction. Each conductive layer in the stack of conductive layers and insulating layers is coupled to a corresponding contact structure of the multiple contact structures and isolated from one or more other contact structures of the multiple contact structures.

Abstract: In some examples, the semiconductor structures include a stack structure, a plurality of conductive structures and a first insulating layer. The stack structure may include a plurality of first dielectric layers and gate layers which are alternately disposed; the stack structure may have a memory region and a connection region, the stack structure in the connection region may include a plurality of first dielectric layers and second dielectric layers. The plurality of conductive structures may be disposed in the connection region. The conductive structure includes conductive portions insulated from each other, each conductive portion penetrates through part of the stack structure and is connected with the gate layers. Parts of the conductive portions that penetrate through the stack structure may be disposed in a nested manner. The semiconductor structure is applied to a three-dimensional memory, so as to implement reading and writing operations of data. Other examples are disclosed.

Abstract: An ultrahigh strain recovery shape memory alloy screen pipe material and a preparation method and application thereof. The material is obtained by cold pressing molding of a preform, the preform is prepared by winding a NiTi shape memory alloy wire into a spiral coil and then winding, laying or weaving, the spiral coil of the NiTi shape memory alloy wire in the preform is structurally embedded or interlocked with each other, and the alloy screen pipe material has a recovery strain of 43-83% at a temperature of 100-350° C. The material has excellent high-temperature tolerance, can achieve spontaneous expansion and deformation under high-temperature conditions, and generally has an ultrahigh recoverable strain. Its pore characteristic is a through-hole structure and a pore size is controllable, so that a filtration effect is ensured, and the preparation cost is relatively low.

Abstract: A disclosed memory device includes transistors. Each transistor includes a semiconductor body extending along a first direction; and a gate structure coupled with the semiconductor body. The gate structure extends along the first direction and includes a first conductive layer extending along the first direction and a second conductive layer in contact with the first conductive layer at the first direction. A first end of the first conductive layer is in contact with a second end of the second conductive layer, and a second end of the first conductive layer is away from the second end of the second conductive layer. A material of the second conductive layer is different from a material of the first conductive layer.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatingly and are formed into stair steps in a staircase region. The semiconductor device includes a first landing pad on a first gate layer of a first stair step. The first gate layer is a top gate layer of the first stair step. The semiconductor device further includes a first sidewall isolation structure on a riser sidewall of a second gate layer of a second stair step. The second gate layer is a top gate layer of the second stair step and is stacked on the first gate layer in the memory stack. The first sidewall isolation structure isolates the second gate layer from the first landing pad.

Abstract: Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a semiconductor layer, a memory stack over the semiconductor layer, first channel structures each extending vertically through the memory stack in an edge region, and an isolation structure. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. At least one of conductive layers toward the semiconductor layer is a source select gate line (SSG). The isolation structure extends vertically through the SSG and into the semiconductor layer. The memory stack includes a core array region, a staircase region, and the edge region being laterally between the core array region and the staircase region. At least one of the first channel structures extends through the isolation structure and is separated from the SSG through the isolation structure.

Abstract: A memory device includes an array of memory cells in an array region and bit lines coupled with the memory cells in the array. The array includes a first sub-array and a second sub-array, and the bit lines extend in a bit line direction. The memory device further includes contact structures in a first connecting region and isolation walls. The contact structures are located between the first sub-array and the second sub-array, and the isolation walls are between the contact structures and the first sub-array, and between the contact structures and the second sub-array.

Abstract: Some implementations of memory devices and fabrication method of the memory devices are provided. One of the memory devices includes an array of memory cells in a memory array area and a plurality of word lines extending, in a first direction, from the memory array area to a connection area. Each memory cell includes a semiconductor body. In the connection area, word-line interconnects extend in a third direction to connect with the plurality of word lines. The plurality of word lines include a first word line and a second word line arranged in a second direction and between two rows of the semiconductor bodies. In the second direction, a first distance between the first word line and the second word line in the connection area is greater than a second distance between the first word line and second word line in the memory array area.

Abstract: A semiconductor device includes decks stacked over a semiconductor layer in a vertical direction. Each deck includes alternating word line layers and insulating layers. A gate line structure (GLS) extends through the word line layers and the insulating layers of the decks. A channel structure extends through the word line layers and the insulating layers of the decks. A sidewall of the GLS is discontinuous at a border between two neighboring decks, and a sidewall of the channel structure is discontinuous at an interface between two neighboring decks. The GLS includes a first GLS that includes a gate line slit, a second GLS that includes sub-GLSs spaced apart from each other in a horizontal direction, or a combination thereof.

Abstract: A sintering apparatus for simultaneously sintering an electronic device onto a substrate, and a metallic sheet onto the electronic device includes a sinter tool and a compressible film positionable onto the metallic sheet and the electronic device. A thickness of the compressible film is greater than a height of the metallic sheet. The compressible film is adapted to conform to a shape of the metallic sheet and the electronic device to simultaneously cover the metallic sheet and at least a part of the electronic device when the sinter tool applies a sintering force onto the compressible film during a sintering process.

Abstract: A heat pump system includes a compressor, a first heat exchanger, a second heat exchanger, and a valve device. The valve device includes a first connecting port connected to an exhaust port of the compressor, a second connecting port connected to a first port of the second heat exchanger, a third connecting port connected to an air suction port of the compressor, a fourth connecting port connected to a first port of the first heat exchanger, and a fifth connecting port connected to a fourth port of the first heat exchanger. In a refrigeration mode, the valve device fluidly couples the third connecting port to the air suction port, and the first heat exchanger operates as a falling film evaporator. In a heating mode, the valve device fluidly couples the first connecting port to the exhaust port, and the first heat exchanger operates as a condenser.

Abstract: Disclosed are a cast 5A duplex stainless steel and a method for preparing a large casting made of this steel. By controlling contents of Cr and Mo elements and meanwhile adding W, Nb, Ce and La elements, precipitation of a brittle phase can be avoided through a coupling effect of the four elements, the precipitation of the brittle phase during a slow cooling process of the large casting is avoided, crack defects of the large casting during a casting process are fundamentally solved, and a finished product rate of the casting can be increased to 95% or above. Meanwhile, with increase of a process yield and implementation of cold mold opening and shakeout, the casting production cost is substantially reduced, safety risks during a production process are greatly reduced, and the labor intensity of workers is reduced.

Abstract: A method of fabricating a three-dimensional memory includes forming a laminated structure including stacked dummy gate layers and interlayer insulation layers on one side of a substrate. The respective adjacent dummy gate layers and interlayer insulation layers form staircase stairs. At least a part of the interlayer insulation layer of each of the staircase stairs is exposed. The method also includes forming a buffer layer covering the staircase stairs. The method further includes removing a part of the buffer layer covering the sidewalls of the staircase stairs to form spacing grooves. The method further includes forming a dielectric layer that fills the spacing grooves and covers the staircase stairs. The method further includes forming a contact hole penetrating through the dielectric layer and the buffer layer and extending to the dummy gate layer farthest from the substrate.

Abstract: A semiconductor device includes a stack of alternating word line layers and insulating layers. The stack includes a core area, a stair step area, and, optionally, a dummy transition area connecting the core area to the stair step area. The semiconductor device also includes a gate line (GL) trench through the stack extending from the core area through the dummy transition area to the stair step area. The GL trench has a first width within the core area and a second width within the stair step area that is different from the first width. The semiconductor device also includes a first channel structure formed through the stack within the core area, and a stair step contact (SCT) formed through at least a portion of the stack within the stair step area. The SCT connects one of the word line layers of the stack within the stair step area.

Abstract: The present disclosure provides a memory device and a manufacturing method thereof. The memory device includes first, second and third semiconductor bodies that each extend in a first and a second direction and are arranged in a third direction, and a first conductive line extending in the third direction. The first and the second semiconductor bodies are located on a same side of two opposite sides of the third semiconductor body in the third direction. The first conductive line is at least located on one of two opposite sides of the first, second and third semiconductor bodies in the second direction. A size of the third semiconductor body in the second direction is greater than a size of the second semiconductor body in the second direction, and is smaller than a size of the first semiconductor body in the second direction.