Abstract: A measurement apparatus (100), which is arranged on a pipe (101), and is configured to measure the liquid content of a medium within the pipe (101); said apparatus comprises: a light transmission member (210), a light generation device (203), and a light reception device (204); the light generation device (203) is configured to emit emission light toward the light transmission member (210) that passes through an outer boundary wall (214) of the light transmission member (210) and has a preset emission angle, and the light reception device (204) is configured to receive reflection light after the emission light is reflected by an inner boundary wall (215) of the light transmission member (210). The measurement apparatus (100) can directly detect whether liquid is carried in a gaseous refrigerant exiting from an evaporator, as well as measure the amount of carried liquid.

Abstract: The present disclosure provides a preparation method of an easy-to-cook whole grain based on microwave-induced cracking, and belongs to the technical field of food processing. In the present disclosure, the preparation method of an easy-to-cook whole grain includes the following steps: subjecting a whole grain to a heat-moisture treatment, and conducting short-time microwave-induced cracking, tempering, and cooling to obtain the easy-to-cook whole grain. The easy-to-cook whole grain obtained by the preparation method of the present disclosure has a complete grain, a slightly-expanded volume, and fine cracks on its surface. Compared with unprocessed whole grains, the easy-to-cook whole grain has a water absorption increased from 1.35 times to 1.9 times an original weight of the unprocessed whole grains during rice steaming.

Abstract: A positive electrode active material includes a core containing Li1+xMn1yAyP1?zRzO4, a first coating layer covering the core and containing a crystalline pyrophosphate MaP2O7 and a crystalline oxide M?bOc, and a second coating layer covering the first coating layer.

Abstract: Provided is a display panel. The display panel includes: a base substrate, a light shielding layer, a buffer layer, an active layer, a gate insulative layer, a gate layer, a first interlayer dielectric layer, and a first conductive layer that are sequentially laminated; wherein the light shielding layer includes a first electrode; the active layer includes a second electrode connected to the first electrode; the gate layer includes a third electrode; and the first conductive layer includes a fourth electrode.

Abstract: A three-dimensional (3D) memory device is provided. In an example, the 3D memory device includes a staircase and a plurality of groups of support structures through the staircase. The plurality of groups of support structures are arranged in a first direction, and each of the groups of support structures comprises three support structures, wherein projections of the three support structures form a triangular shape in a plane parallel to the first direction.

Abstract: A light-emitting device, a light-emitting substrate, and a method for manufacturing the light-emitting device. The light-emitting device includes at least one light-emitting structure. The light-emitting structure includes: a first semiconductor layer; a light-emitting layer; a second semiconductor layer, doping ions of the second semiconductor layer and a first semiconductor layer being oppositely charged; a barrier structure provided with an opening for exposing the second semiconductor layer, the orthographic projection of the opening on the base substrate being located in the orthographic projection of the light-emitting layer on the base substrate, and the area of the opening being smaller than that of the light-emitting layer; and a landing electrode located on the side of the barrier structure facing away from the second semiconductor layer, the landing electrode being in contact with the second semiconductor layer by means of the opening.

Abstract: A well cementing method is described for improving cementing quality by controlling the hydration heat of cement slurry. By controlling the degree and/or rate of hydration heat release from cement slurry, the method improves the hydration heat release during formation of cement with curing of cement slurry, improves the binding quality between the cement and the interfaces, and in turn improves the cementing quality at the open hole section and/or the overlap section. The cementing method improves cementing quality of oil and gas wells and reduces the risk of annular pressure.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatingly and are formed into stair steps in a staircase region. The semiconductor device includes a first landing pad on a first gate layer of a first stair step. The first gate layer is a top gate layer of the first stair step. The semiconductor device further includes a first sidewall isolation structure on a riser sidewall of a second gate layer of a second stair step. The second gate layer is a top gate layer of the second stair step and is stacked on the first gate layer in the memory stack. The first sidewall isolation structure isolates the second gate layer from the first landing pad.

Abstract: A non-road mobile machinery (NRMM) is provided and includes a fuel storage device, a fuel supply device, a vapor adsorption device, and an engine body. The vapor adsorption device is provided with an air vent communicated to the atmosphere. A vapor discharge hole of the fuel storage device is communicated to an adsorption vent of the vapor adsorption device. The NRMM also includes a valve mechanism connected between a desorption vent of the vapor adsorption device and an intake channel of the engine body. The valve mechanism is conducted with the working of the engine body and blocked with the stop of the engine body. The NRMN improves the evaporation emission performance of the NRMM when compared to the prior art and solves the problem that the evaporation emissions of the NRMM in the prior art are prone to exceed the standard.

Abstract: Provided are a method and apparatus for evaluating image relative definition, a device and a medium, relating to technologies such as computer vision, deep learning and intelligent medical. A specific implementation solution is: extracting a multi-scale feature of each image in an image set, where the multi-scale feature is used for representing definition features of objects having different sizes in an image; and scoring relative definition of each image in the image set according to the multi-scale feature by using a relative definition scoring model pre-trained, where the purpose for training the relative definition scoring model is to learn a feature related to image definition in the multi-scale feature.

Abstract: A wafer-level assembly method for a micro hemispherical resonator gyroscope includes: after independently manufactured glass substrates are softened and deformed at a high temperature, forming a micro hemispherical resonator on the glass substrate; forming glass substrate alignment holes at both ends of the glass substrate by laser ablation; aligning and fixing a plurality of identical micro hemispherical resonators on a wafer fixture by using the alignment holes as a reference, and then performing operations by using the wafer fixture as a unit to implement subsequent processes that include: releasing the micro hemispherical resonators, metallizing the surface, fixing to the planar electrode substrates, separating the wafer fixture and cleaning to obtain a micro hemispherical resonator gyroscope driven by a bottom planar electrode substrate.

Abstract: The present disclosure provides methods, compositions, kits and systems for nucleic acid amplification. In some embodiments, nucleic acid amplification methods include subjecting the nucleic acid to be amplified to partially denaturing conditions. In some embodiments, nucleic acid amplification methods include amplifying without fully denaturing the nucleic acid that is amplified. In some embodiments, the nucleic acid amplification method employs an enzyme that catalyzes homologous recombination and a polymerase. In some embodiments, methods for nucleic acid amplification can be conducted in a single reaction vessel and/or in a single continuous liquid phase of a reaction mixture, without need for compartmentalization of the reaction mixture or immobilization of reaction components.

Abstract: A fan, comprising blades (102), an upper hub (111), and a lower hub (112). Each blade (102) comprises a connecting part (211). The connecting part (211) is clamped between a lower surface of the upper hub (111) and an upper surface of the lower hub (112). The lower surface of the upper hub (111) is provided with an upper hub connecting area, and the upper surface of the lower hub (112) is provided with a lower hub connecting area. An upper surface and a lower surface of the connecting part (211) are separately provided with a junction surface extending from the connecting part (211). The lower surface of the upper hub (111) and the upper surface of the lower hub (112) are separately provided with a matching surface matching the junction surface.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatingly and are formed into stair steps in a staircase region. Further, the semiconductor device includes a landing stack formed on the stair steps in the staircase region. The landing stack includes an upper layer that is etch selective to a contact isolation layer that covers the staircase region. Then, the semiconductor device includes a first contact structure on a first stair step of the stair steps. The first contact structure extends through a first contact hole in the contact isolation layer and the landing stack. The first contact structure is connected with a first gate layer (e.g., a top gate layer) of the first stair step.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers, a landing structure and a contact structure. The gate layers and the insulating layers are stacked alternatingly, and form stair steps in a staircase region. The landing structure is disposed on a first gate layer of a first stair step of the stair steps in the staircase region. The landing structure includes an upper structure and an isolation stack between the upper structure and the first gate layer. The upper structure is etch-selective to a contact isolation layer that covers the staircase region. The contact structure extends through the contact isolation layer and the landing structure and is connected with the first gate layer of the first stair step.

Abstract: A sintering apparatus for simultaneously sintering an electronic device onto a substrate, and a metallic sheet onto the electronic device includes a sinter tool and a compressible film positionable onto the metallic sheet and the electronic device. A thickness of the compressible film is greater than a height of the metallic sheet. The compressible film is adapted to conform to a shape of the metallic sheet and the electronic device to simultaneously cover the metallic sheet and at least a part of the electronic device when the sinter tool applies a sintering force onto the compressible film during a sintering process.

Abstract: Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a semiconductor layer, a memory stack over the semiconductor layer, first channel structures each extending vertically through the memory stack in an edge region, and an isolation structure. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. At least one of conductive layers toward the semiconductor layer is a source select gate line (SSG). The isolation structure extends vertically through the SSG and into the semiconductor layer. The memory stack includes a core array region, a staircase region, and the edge region being laterally between the core array region and the staircase region. At least one of the first channel structures extends through the isolation structure and is separated from the SSG through the isolation structure.

Abstract: A method of preparing a functionalized electrode array is provided. The method includes depositing a conductive material onto the surface of a substrate by droplet-based printing of particles comprising an electrically-conductive material. The surface of the conductive material is functionalized with a binding reagent that binds to an analyte. A three-dimensional electrode array and microfluidic test device are also provided.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.

Abstract: According to embodiments of the present invention, an apparatus is provided. The apparatus includes a relief valve having an inlet pathway arranged to receive a medium flowing in the apparatus, and an outlet pathway arranged for the medium from the inlet pathway to flow through at a relief state to relieve pressure in the apparatus, an outlet pressure sensor arranged to determine an outlet pressure associated with the outlet pathway, and a processing circuit configured to determine a status of the relief valve based on the outlet pressure.