Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatingly and are formed into stair steps in a staircase region. The semiconductor device includes a first landing pad on a first gate layer of a first stair step. The first gate layer is a top gate layer of the first stair step. The semiconductor device further includes a first sidewall isolation structure on a riser sidewall of a second gate layer of a second stair step. The second gate layer is a top gate layer of the second stair step and is stacked on the first gate layer in the memory stack. The first sidewall isolation structure isolates the second gate layer from the first landing pad.

Abstract: Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a semiconductor layer, a memory stack over the semiconductor layer, first channel structures each extending vertically through the memory stack in an edge region, and an isolation structure. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. At least one of conductive layers toward the semiconductor layer is a source select gate line (SSG). The isolation structure extends vertically through the SSG and into the semiconductor layer. The memory stack includes a core array region, a staircase region, and the edge region being laterally between the core array region and the staircase region. At least one of the first channel structures extends through the isolation structure and is separated from the SSG through the isolation structure.

Abstract: A memory device includes an array of memory cells in an array region and bit lines coupled with the memory cells in the array. The array includes a first sub-array and a second sub-array, and the bit lines extend in a bit line direction. The memory device further includes contact structures in a first connecting region and isolation walls. The contact structures are located between the first sub-array and the second sub-array, and the isolation walls are between the contact structures and the first sub-array, and between the contact structures and the second sub-array.

Abstract: Some implementations of memory devices and fabrication method of the memory devices are provided. One of the memory devices includes an array of memory cells in a memory array area and a plurality of word lines extending, in a first direction, from the memory array area to a connection area. Each memory cell includes a semiconductor body. In the connection area, word-line interconnects extend in a third direction to connect with the plurality of word lines. The plurality of word lines include a first word line and a second word line arranged in a second direction and between two rows of the semiconductor bodies. In the second direction, a first distance between the first word line and the second word line in the connection area is greater than a second distance between the first word line and second word line in the memory array area.

Abstract: A semiconductor device includes decks stacked over a semiconductor layer in a vertical direction. Each deck includes alternating word line layers and insulating layers. A gate line structure (GLS) extends through the word line layers and the insulating layers of the decks. A channel structure extends through the word line layers and the insulating layers of the decks. A sidewall of the GLS is discontinuous at a border between two neighboring decks, and a sidewall of the channel structure is discontinuous at an interface between two neighboring decks. The GLS includes a first GLS that includes a gate line slit, a second GLS that includes sub-GLSs spaced apart from each other in a horizontal direction, or a combination thereof.

Abstract: A sintering apparatus for simultaneously sintering an electronic device onto a substrate, and a metallic sheet onto the electronic device includes a sinter tool and a compressible film positionable onto the metallic sheet and the electronic device. A thickness of the compressible film is greater than a height of the metallic sheet. The compressible film is adapted to conform to a shape of the metallic sheet and the electronic device to simultaneously cover the metallic sheet and at least a part of the electronic device when the sinter tool applies a sintering force onto the compressible film during a sintering process.

Abstract: A heat pump system includes a compressor, a first heat exchanger, a second heat exchanger, and a valve device. The valve device includes a first connecting port connected to an exhaust port of the compressor, a second connecting port connected to a first port of the second heat exchanger, a third connecting port connected to an air suction port of the compressor, a fourth connecting port connected to a first port of the first heat exchanger, and a fifth connecting port connected to a fourth port of the first heat exchanger. In a refrigeration mode, the valve device fluidly couples the third connecting port to the air suction port, and the first heat exchanger operates as a falling film evaporator. In a heating mode, the valve device fluidly couples the first connecting port to the exhaust port, and the first heat exchanger operates as a condenser.

Abstract: Disclosed are a cast 5A duplex stainless steel and a method for preparing a large casting made of this steel. By controlling contents of Cr and Mo elements and meanwhile adding W, Nb, Ce and La elements, precipitation of a brittle phase can be avoided through a coupling effect of the four elements, the precipitation of the brittle phase during a slow cooling process of the large casting is avoided, crack defects of the large casting during a casting process are fundamentally solved, and a finished product rate of the casting can be increased to 95% or above. Meanwhile, with increase of a process yield and implementation of cold mold opening and shakeout, the casting production cost is substantially reduced, safety risks during a production process are greatly reduced, and the labor intensity of workers is reduced.

Abstract: A method of fabricating a three-dimensional memory includes forming a laminated structure including stacked dummy gate layers and interlayer insulation layers on one side of a substrate. The respective adjacent dummy gate layers and interlayer insulation layers form staircase stairs. At least a part of the interlayer insulation layer of each of the staircase stairs is exposed. The method also includes forming a buffer layer covering the staircase stairs. The method further includes removing a part of the buffer layer covering the sidewalls of the staircase stairs to form spacing grooves. The method further includes forming a dielectric layer that fills the spacing grooves and covers the staircase stairs. The method further includes forming a contact hole penetrating through the dielectric layer and the buffer layer and extending to the dummy gate layer farthest from the substrate.

Abstract: The present disclosure provides a memory device and a manufacturing method thereof. The memory device includes first, second and third semiconductor bodies that each extend in a first and a second direction and are arranged in a third direction, and a first conductive line extending in the third direction. The first and the second semiconductor bodies are located on a same side of two opposite sides of the third semiconductor body in the third direction. The first conductive line is at least located on one of two opposite sides of the first, second and third semiconductor bodies in the second direction. A size of the third semiconductor body in the second direction is greater than a size of the second semiconductor body in the second direction, and is smaller than a size of the first semiconductor body in the second direction.

Abstract: A semiconductor device includes a stack of alternating word line layers and insulating layers. The stack includes a core area, a stair step area, and, optionally, a dummy transition area connecting the core area to the stair step area. The semiconductor device also includes a gate line (GL) trench through the stack extending from the core area through the dummy transition area to the stair step area. The GL trench has a first width within the core area and a second width within the stair step area that is different from the first width. The semiconductor device also includes a first channel structure formed through the stack within the core area, and a stair step contact (SCT) formed through at least a portion of the stack within the stair step area. The SCT connects one of the word line layers of the stack within the stair step area.

Abstract: A measurement apparatus arranged on a pipe is configured to measure liquid content of a medium within the pipe. The apparatus includes a light transmission member, a light generation device, and a light reception device. The light generation device is configured to emit emission light toward the light transmission member such that it passes through an outer boundary wall of the light transmission member and has a preset emission angle. The light reception device is configured to receive reflection light after the emission light is reflected by an inner boundary wall of the light transmission member. The measurement apparatus can detect whether liquid is carried in a gaseous refrigerant exiting from an evaporator and measure the amount of carried liquid. The refrigeration system can adjust a throttling apparatus according to a measured result, and prevents the performance of the refrigeration system and a compressor from being affected.

Abstract: A privilege providing system includes a first processor to recognize a prescribed act; a second processor to grant a privilege to at least a subject other than a performer of the prescribed act upon the act being recognized by the first processor, and a storage configured to store the privilege granted by the second processor to at least the subject other than the performer of the prescribed act.

Abstract: Memory devices and fabricating methods thereof are provided. A disclosed memory device comprises an array of transistors, an array of capacitors, and an array of contact structures connected between the array of transistors and the array of capacitors. Each transistor comprises a semiconductor body extending along a vertical direction. Gate structures of adjacent transistors are laterally separated from each other by an insulating layer having a first material. Each contact structure is aligned with a corresponding semiconductor body in the vertical direction. Adjacent contact structures are laterally separated from each other by a protection layer having a second material different from the first material. Each capacitor is in contact with a corresponding one of the array of contact structures.

Abstract: The present application discloses a blade and an axial-flow impeller using the same. The present application provides a blade, comprising a blade tip, a blade root, a leading edge and a trailing edge, wherein the leading edge and the trailing edge extend from the blade tip to the blade root, respectively. The blade is capable of rotating about a rotation axis X which is perpendicular to a normal plane. In a projection of the blade on the normal plane, a circumferential included angle between the leading edge and the trailing edge forms a wrap angle, and the wrap angle decreases gradually from the blade root to a middle blade height of the blade and increases gradually from the middle blade height to the blade tip. Wherein, the middle blade height is an arc line formed by center points of the blade tip and the blade root along a radial direction.

Abstract: Three-dimensional micro-supercapacitors and methods for fabrication of micro-supercapacitors are provided. A micro-supercapacitor embodiment includes a three-dimensional electrode with self-supporting layers of two-dimensional nanomaterial. A method embodiment includes using non-contact 3D printing to generate a micro-supercapacitor, including a three-dimensional electrode having self-supporting two-dimensional nanomaterial.

Abstract: A semiconductor device includes a stack of alternating word line layers and insulating layers. The stack includes a core area, a stair step area, and, optionally, a dummy transition area connecting the core area to the stair step area. The semiconductor device also includes a gate line (GL) trench through the stack extending from the core area through the dummy transition area to the stair step area. The GL trench has a first width within the core area and a second width within the stair step area that is different from the first width. The semiconductor device also includes a first channel structure formed through the stack within the core area, and a stair step contact (SCT) formed through at least a portion of the stack within the stair step area. The SCT connects one of the word line layers of the stack within the stair step area.

Abstract: According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a semiconductor structure including a semiconductor body extending along a first direction. The semiconductor device may include a conductive structure located on a side of the semiconductor body along the first direction. The conductive structure may include a first part and a second part arranged along a second direction. The first part may be in contact with an end of the semiconductor body. A size of a portion of the first part close to the second part in a third direction may be different from a size of a portion of the second part close to the first part in the third direction. The second direction may intersect the third direction, and the first direction may be perpendicular to a plane formed by the second direction and the third direction.

Abstract: The examples of the present disclosure provide a semiconductor device and a manufacturing method. One example method includes: forming a plurality of conductive structures; forming a plurality of semiconductor bodies, wherein the semiconductor bodies are located on one side of the conductive structures along a first direction and are connected to the conductive structures; forming a first dielectric layer, wherein the first dielectric layer is located between the plurality of conductive structures; forming a second dielectric layer, wherein the second dielectric layer is located between the plurality of semiconductor bodies; and forming a third dielectric layer, wherein the third dielectric layer is located between the first dielectric layer and the second dielectric layer.

Abstract: Semiconductor devices, fabrication methods of such semiconductor devices, systems including such semiconductor devices are provided. In one aspect, a fabrication method of a semiconductor device includes: forming a conductive structure having a first surface and a second surface opposite to each other along a first direction, the conductive structure including at least a metal semiconductor compound layer extending along the first direction; forming a semiconductor body located on the first surface of the conductive structure and connected with the metal semiconductor compound layer; and forming a storage structure located on the second surface of the conductive structure and connected with the metal semiconductor compound layer.