Abstract: A three-dimensional (3D) memory device includes a staircase, a plurality of contacts, and a plurality of groups of support structures through the staircase. The plurality of groups of support structures are arranged in a first direction. Each of the groups of support structures includes support structures. The plurality of contacts each is surrounded by a respective group. A projection of one of the contacts overlaps with a shape of the respective group. A distance between two support structures in each of the groups is in a range of about 350 to about 500 nm.

Abstract: A non-road engine is provided. The non-road engine includes a carburetor and a combination switch for controlling on-off of a fuel supply pipe between a fuel tank and the carburetor, where the carburetor is provided with a control valve for controlling opening and closing of a main jet; the control valve is linked and matched with the combination switch; when the combination switch is in an on state, the control valve causes the main jet to be in an open state; and when the combination switch is in an off state, the control valve causes the main jet to be in a closed state.

Abstract: The present disclosure relates methods, devices, systems, and techniques for merging schemes in semiconductor devices such as three-dimensional (3D) semiconductor devices. In one aspect, a semiconductor device includes a semiconductor structure that includes a stack of conductive layers and insulating layers alternating with each other along a first direction. The semiconductor structure includes an array region and a connection region adjacent to the array region in a second direction perpendicular to the first direction. The semiconductor device further includes multiple contact structures extending through the connection region along the first direction. Each conductive layer in the stack of conductive layers and insulating layers is coupled to a corresponding contact structure of the multiple contact structures and isolated from one or more other contact structures of the multiple contact structures.

Abstract: A gate drive circuit includes a plurality of gate drive units. Each of the gate drive units includes a stage transmission signal selection circuit, a pull-up control circuit, a pulse number reduction circuit, a first inversion circuit, a first output stage, and a second output stage, and can output a second gate control signal with a greater number of pulses and a first gate control signal with a less number of pulses. At least one of the stage transmission signal selection circuit, the first inversion circuit or the second output stage includes three transistors with the same channel type.

Abstract: The present disclosure relates to a system and method for vulnerability localization based on deep learning, which comprises, at a minimum, a processor configured to: analyze a code file under detection to obtain a first abstract syntax tree devoid of semantic information; build upon the first abstract syntax tree by incorporating data-flow edges and/or control-flow edges, thereby forming a second abstract syntax tree with semantic-flow enhancement; split the second abstract syntax tree to obtain a plurality of second abstract syntax sub-trees; and input these second abstract syntax sub-trees into a pre-established vulnerability detection and localization model.

Abstract: A non-road engine is provided. The non-road engine includes a carburetor and a combination switch for controlling on-off of a fuel supply pipe between a fuel tank and the carburetor, where the carburetor is provided with a control valve for controlling opening and closing of a main jet; the control valve is linked and matched with the combination switch; when the combination switch is in an on state, the control valve causes the main jet to be in an open state; and when the combination switch is in an off state, the control valve causes the main jet to be in a closed state.

Abstract: The present disclosure discloses a gate drive circuit and a display panel. The gate drive circuit includes a plurality of shift registers. Each shift register includes a level transmission signal selection module, a pull-up control module, a pulse quantity reduction module, a first inverting module, a first output module, a second output module, and a voltage boosting module. By connecting the voltage boosting module between a second electrode of a second transistor and a low potential line in series, when a first transistor is turned on, a potential of the second electrode of the second transistor can be increased, and on-state current of the second transistor can be reduced, so that a pulse amplitude of a second gate drive signal can be increased and stabilized.

Abstract: A method for forming a memory device is disclosed. A stack structure including interleaved first layers and second layers is formed. A staircase structure including stairs at an edge of the stack structure is formed. Each stair has one of the first layers on a top surface of the stair. A third layer including vertical portions covering side surface of the stairs and lateral portions covering the top surface of the stairs is formed. The third layer includes a first sublayer in contact with the stair and a second sublayer in contact with the first sublayer and on the first sublayer. A mask covering the vertical portions and the lateral portions of the third layer is formed. A portion of the mask covering the vertical portions of the third layer is removed to expose the vertical portions of the third layer. Vertical portions of the first sublayer are removed using a first etching process. Vertical portions of the second sublayer are removed using a second etching process.

Abstract: Structures of a three-dimensional (3D) memory device and systems containing the same are disclosed. In one example, the 3D memory device includes a memory plane, where the memory plane includes a first edge and an array of blocks. The array of blocks includes a plurality of memory blocks configured to store data, where the plurality of memory blocks are separated by continuous slit structures, and a first dummy region between the first edge and the plurality of memory blocks. The first dummy region includes alternating first slit structures and second slit structures, where the first slit structures and the second slit structures are discontinuous slit structures.

Abstract: Disclosed herein is a memory device that includes a stack structure. The stack structure has alternating first layers and dielectric layers. The stack structure has a first surface and a second surface opposite to the first surface. First contact structures include a conductive material. The first contact structures penetrate from the first surface into the stack structure to be in contact respectively with a first portion of first layers. Second contact structures include a conductive material. Each of the second contact structures penetrates from the second surface into the stack structure to be in contact respectively with a remainder portion of conductive layers other than the first portion of the first layers.

Abstract: Aspects of the disclosure provide methods for fabricating semiconductor devices. In some examples, a method for fabricating a semiconductor device includes forming a stack of layers having a first region and a second region. The stack of layers includes at least a first layer. The method then forms a hard mask layer on the stack of layers in the first region. Then, the method includes patterning the stack of layers in the second region of the semiconductor device. The patterning of the stack of layers in the second region removes a portion of the stack of layers in the second region, and exposes a side of the stack of layers. The method further includes covering at least the side of the stack of layers with a second layer that has a lower remove rate than the first layer, and then the method includes removing the hard mask layer.

Abstract: The present disclosure is directed to simple, scalable methods of forming colloidal MXene dispersions in nonpolar organic solvents with long term stability.

Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory. In an example, the method includes forming a stack structure having interleaved a plurality of stack first layers and a plurality of stack second layers, forming a stair in the stack structure, the stair having one of the stack first layers on a top surface, and forming a layer of sacrificial material having a first portion over a side surface of the stair and a second portion over the top surface of the stair. The method also includes partially removing the first portion of the layer of sacrificial material using an anisotropic etching process and removing a remaining portion of the first portion of the layer of sacrificial material using an isotropic etching process.

Abstract: A catalyst for gas-phase oxidation of 1,2,4,5-tetraalkylbenzene to prepare benzene-1,2,4,5-tetracarboxylic dianhydride, a preparation method for and an application of the catalyst, and a preparation method for benzene-1,2,4,5-tetracarboxylic dianhydride are disclosed. The catalyst according to the present invention comprises a carrier and a catalytically active component coating attached to the carrier; the catalytically active component coating comprises a first coating and a second coating; the first coating is close to the surface of the carrier, and the second coating is distant from the surface of the carrier; in the first coating, the mass ratio of a titanium element denoted by Ti to a vanadium element denoted by V is Ti/V1; in the second coating, the mass ratio of the titanium element denoted by Ti to the vanadium element denoted by V is Ti/V2, wherein Ti/V2=Ti/V1+?Ti/V, and ?Ti/V is within a range of 3 to 9.

Abstract: A method and system for recognizing TLS fingerprints based on finite-state machines is provided, wherein the system at least includes: a model inference module, for learning state machine models of target TLS implementations according to mapping information sent by a message mapping module; a fingerprint extracting module, for analyzing the state machine models and extracting multi-level fingerprints of the target TLS implementations; and a version recognizing module, for verifying the multi-level fingerprints for validity and/or recognizing version information of unknown TLS implementations. As compared to other network protocol identification systems, the present disclosure can identify and judge fine-grained information such as the specific implementation type and version of the specific TLS implementation. At the same time, the inventive method is highly automated, thereby ensuring good usability and scalability.

Abstract: A gate drive circuit includes a plurality of gate drive units. Each of the gate drive units includes a stage transmission signal selection circuit, a pull-up control circuit, a pulse number reduction circuit, a first inversion circuit, a first output stage, and a second output stage, and can output a second gate control signal with a greater number of pulses and a first gate control signal with a less number of pulses. At least one of the stage transmission signal selection circuit, the first inversion circuit or the second output stage includes three transistors with the same channel type.

Abstract: The present invention provides methods and compositions for treating or preventing breast cancer with S-equol. The method and compositions are particularly suited to treating triple-negative breast cancer. The S-equol may be administered alone or in combination with one or more cytotoxic or immunotherapeutic compound or molecule.

Abstract: The present invention provides methods and compositions for modulating molecular markers, and hence treating or preventing breast cancer (e.g., triple-negative breast cancer) and melanoma with a pharmaceutically effective amount of S-equol or a pharmaceutical composition comprising S-equol. The S-equol may be administered alone or in combination with one or more cytotoxic or immunotherapeutic compound or molecule.

Abstract: The present invention provides methods and compositions for treating or preventing melanoma with S-equol. The S-equol may be administered alone or in combination with one or more cytotoxic or immunotherapeutic compound or molecule.

Abstract: A fan, comprising blades (102), an upper hub (111), and a lower hub (112). Each blade (102) comprises a connecting part (211). The connecting part (211) is clamped between a lower surface of the upper hub (111) and an upper surface of the lower hub (112). The lower surface of the upper hub (111) is provided with an upper hub connecting area, and the upper surface of the lower hub (112) is provided with a lower hub connecting area. An upper surface and a lower surface of the connecting part (211) are separately provided with a junction surface extending from the connecting part (211). The lower surface of the upper hub (111) and the upper surface of the lower hub (112) are separately provided with a matching surface matching the junction surface.