Patents by Inventor Biswajeet Guha
Biswajeet Guha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12230717Abstract: Integrated circuit structures having partitioned source or drain contact structures, and methods of fabricating integrated circuit structures having partitioned source or drain contact structures, are described. For example, an integrated circuit structure includes a fin. A gate stack is over the fin. A first epitaxial source or drain structure is at a first end of the fin. A second epitaxial source or drain structure is at a second end of the fin. A conductive contact structure is coupled to one of the first or the second epitaxial source or drain structures. The conductive contact structure has a first portion partitioned from a second portion.Type: GrantFiled: February 23, 2023Date of Patent: February 18, 2025Assignee: Intel CorporationInventors: Mauro J. Kobrinsky, Stephanie Bojarski, Babita Dhayal, Biswajeet Guha, Tahir Ghani
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Patent number: 12230721Abstract: Gate-all-around integrated circuit structures having asymmetric source and drain contact structures, and methods of fabricating gate-all-around integrated circuit structures having asymmetric source and drain contact structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a fin. A gate stack is over the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. A first conductive contact structure is coupled to the first epitaxial source or drain structure. A second conductive contact structure is coupled to the second epitaxial source or drain structure. The second conductive contact structure is deeper along the fin than the first conductive contact structure.Type: GrantFiled: September 18, 2023Date of Patent: February 18, 2025Assignee: Intel CorporationInventors: Biswajeet Guha, Mauro J. Kobrinsky, Tahir Ghani
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Patent number: 12224350Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.Type: GrantFiled: September 29, 2023Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Biswajeet Guha, William Hsu, Leonard P. Guler, Dax M. Crum, Tahir Ghani
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Publication number: 20250048698Abstract: Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures includes vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures includes vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires. A conductive contact structure is laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures.Type: ApplicationFiled: October 22, 2024Publication date: February 6, 2025Inventors: Cory BOMBERGER, Anand MURTHY, Mark T. BOHR, Tahir GHANI, Biswajeet GUHA
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Patent number: 12211925Abstract: Gate-all-around integrated circuit structures having oxide sub-fins, and methods of fabricating gate-all-around integrated circuit structures having oxide sub-fins, are described. For example, an integrated circuit structure includes an oxide sub-fin structure having a top and sidewalls. An oxidation catalyst layer is on the top and sidewalls of the oxide sub-fin structure. A vertical arrangement of nanowires is above the oxide sub-fin structure. A gate stack is surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.Type: GrantFiled: July 10, 2023Date of Patent: January 28, 2025Inventors: Leonard P. Guler, Biswajeet Guha, Tahir Ghani, Swaminathan Sivakumar
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Patent number: 12206027Abstract: Gate-all-around integrated circuit structures having nanowires with tight vertical spacing, and methods of fabricating gate-all-around integrated circuit structures having nanowires with tight vertical spacing, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires. A vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers. A gate stack is around the vertical arrangement of horizontal silicon nanowires. A first source or drain structure is at a first end of the vertical arrangement of horizontal silicon nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal silicon nanowires.Type: GrantFiled: July 31, 2023Date of Patent: January 21, 2025Assignee: Intel CorporationInventors: Glenn Glass, Anand Murthy, Biswajeet Guha, Tahir Ghani, Susmita Ghose, Zachary Geiger
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Patent number: 12199143Abstract: Gate-all-around integrated circuit structures having a removed substrate, and methods of fabricating gate-all-around integrated circuit structures having a removed substrate, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires. A pair of non-discrete epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is between the pair of non-discrete epitaxial source or drain structures and the gate stack. The pair of dielectric spacers and the gate stack have co-planar top surfaces. The pair of dielectric spacers, the gate stack and the pair of non-discrete epitaxial source or drain structures have co-planar bottom surfaces.Type: GrantFiled: December 26, 2019Date of Patent: January 14, 2025Assignee: Intel CorporationInventors: Biswajeet Guha, Mauro Kobrinsky, Patrick Morrow, Oleg Golonzka, Tahir Ghani
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Patent number: 12176429Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.Type: GrantFiled: October 12, 2023Date of Patent: December 24, 2024Assignee: Intel CorporationInventors: Rishabh Mehandru, Tahir Ghani, Stephen Cea, Biswajeet Guha
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Patent number: 12166031Abstract: Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal.Type: GrantFiled: December 22, 2020Date of Patent: December 10, 2024Assignee: Intel CorporationInventors: Biswajeet Guha, Brian Greene, Daniel Schulman, William Hsu, Chung-Hsun Lin, Curtis Tsai, Kevin Fischer
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Patent number: 12159901Abstract: Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures includes vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures includes vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires. A conductive contact structure is laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures.Type: GrantFiled: November 7, 2022Date of Patent: December 3, 2024Assignee: Intel CorporationInventors: Cory Bomberger, Anand Murthy, Mark T. Bohr, Tahir Ghani, Biswajeet Guha
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Publication number: 20240363628Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.Type: ApplicationFiled: July 9, 2024Publication date: October 31, 2024Inventors: Leonard P. GULER, William HSU, Biswajeet GUHA, Martin WEISS, Apratim DHAR, William T. BLANTON, John H. IRBY, IV, James F. BONDI, Michael K. HARPER, Charles H. WALLACE, Tahir GHANI, Benedict A. SAMUEL, Stefan DICKERT
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Publication number: 20240355903Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.Type: ApplicationFiled: July 3, 2024Publication date: October 24, 2024Inventors: Biswajeet GUHA, Dax M. CRUM, Stephen M. CEA, Leonard P. GULER, Tahir GHANI
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Publication number: 20240355876Abstract: Described herein are nanoribbon-based transistors with a highly uniform oxide layer around semiconductor nanoribbon channels, and a high-pressure steam process for growth the oxide layer. The high-pressure steam process is a self-limiting process that results in a more uniform oxide than standard deposition or implantation methods. The uniformity enables greater control over oxide thickness, with improved breakdown voltages and drive currents.Type: ApplicationFiled: April 20, 2023Publication date: October 24, 2024Applicant: Intel corporationInventors: Siddharth Gupta, Robin Chao, Jay Prakash Gupta, Aravind Killampalli, Biswajeet Guha
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Publication number: 20240347539Abstract: Integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the STI structure. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.Type: ApplicationFiled: June 24, 2024Publication date: October 17, 2024Inventors: Tahir GHANI, Mohit K. HARAN, Mohammad HASAN, Biswajeet GUHA, Alison V. DAVIS, Leonard P. GULER
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Publication number: 20240347595Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.Type: ApplicationFiled: January 11, 2024Publication date: October 17, 2024Inventors: William HSU, Biswajeet GUHA, Leonard GULER, Souvik CHAKRABARTY, Jun Sung KANG, Bruce BEATTIE, Tahir GHANI
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Publication number: 20240321987Abstract: Described herein are integrated circuit devices that include both nanoribbon-based transistors and fin-shaped transistors. The nanoribbon transistors may have shorter channel lengths than the fin transistors. In addition, the nanoribbon transistors may have thinner gate dielectrics than the fin transistors.Type: ApplicationFiled: March 22, 2023Publication date: September 26, 2024Applicant: Intel CorporationInventors: Tao Chu, Guowei Xu, Robin Chao, Chiao-Ti Huang, Feng Zhang, Minwoo Jang, Chia-Ching Lin, Biswajeet Guha, Yue Zhong, Anand S. Murthy
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Publication number: 20240304619Abstract: An IC device includes a backside FTI separating a first transistor from a second transistor. The FTI may be between a source region of the first transistor and a drain region of the second transistor. The source region of the first transistor and the drain region of the second transistor may be different portions of a semiconductor structure, e.g., a fin or nanoribbon. The IC device may also include a frontside metal layer. The semiconductor structure may have a first surface and a second surface opposing the first surface. The first surface of the semiconductor structure may be closer to the metal layer and larger than the second surface of the semiconductor structure. The FTI may have a first surface and a second surface opposing the first surface. The first surface of the FTI may be closer to the metal layer but smaller than the second surface of the FTI.Type: ApplicationFiled: March 9, 2023Publication date: September 12, 2024Inventors: Guowei Xu, Chiao-Ti Huang, Robin Chao, Tao Chu, Feng Zhang, Yang Zhang, Biswajeet Guha, Oleg Golonzka
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Publication number: 20240304621Abstract: Fabrication method for nanoribbon-based transistors and associated transistor arrangements, IC structures, and devices are disclosed. An example fabrication method is based on patterning a foundation over which a superlattice is provided so that a single superlattice may be used to form both PMOS and NMOS stacks of nanoribbons. An example IC structure includes a support, an NMOS stack of nanoribbons stacked vertically above one another over the support, and a PMOS stack of nanoribbons stacked vertically above one another over the support, wherein at least one of the nanoribbons of the NMOS stack is vertically offset with respect to at least one of the nanoribbons of the PMOS stack.Type: ApplicationFiled: March 10, 2023Publication date: September 12, 2024Applicant: Intel CorporationInventors: Chiao-Ti Huang, Tao Chu, Robin Chao, Guowei Xu, Feng Zhang, Biswajeet Guha, Stephen M. Cea
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Publication number: 20240290788Abstract: A metal gate fabrication method for nanoribbon-based transistors and associated transistor arrangements, IC structures, and devices are disclosed. An example IC structure fabricated using metal gate fabrication method described herein may include a first stack of N-type nanoribbons, a second stack of P-type nanoribbons, a first gate region enclosing portions of the nanoribbons of the first stack and including an NWF material between adjacent nanoribbons of the first stack, and a second gate region enclosing portions of the nanoribbons of the second stack and including a PWF material between adjacent nanoribbons of the second stack, where the second gate region includes the PWF material at sidewalls of the nanoribbons of the second stack and further includes the NWF material so that the PWF material is between the sidewalls of the nanoribbons of the second stack and the NWF material.Type: ApplicationFiled: February 28, 2023Publication date: August 29, 2024Applicant: Intel CorporationInventors: Guowei Xu, Tao Chu, Chiao-Ti Huang, Robin Chao, David Towner, Orb Acton, Omair Saadat, Feng Zhang, Dax M. Crum, Yang Zhang, Biswajeet Guha, Oleg Golonzka, Anand S. Murthy
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Patent number: 12068314Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.Type: GrantFiled: September 18, 2020Date of Patent: August 20, 2024Assignee: Intel CorporationInventors: Leonard P. Guler, William Hsu, Biswajeet Guha, Martin Weiss, Apratim Dhar, William T. Blanton, John H. Irby, IV, James F. Bondi, Michael K. Harper, Charles H. Wallace, Tahir Ghani, Benedict A. Samuel, Stefan Dickert