Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.

Abstract: Gate-all-around integrated circuit structures having nanowires with tight vertical spacing, and methods of fabricating gate-all-around integrated circuit structures having nanowires with tight vertical spacing, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires. A vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers. A gate stack is around the vertical arrangement of horizontal silicon nanowires. A first source or drain structure is at a first end of the vertical arrangement of horizontal silicon nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal silicon nanowires.

Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.

Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.

Abstract: Gate-all-around integrated circuit structures having oxide sub-fins, and methods of fabricating gate-all-around integrated circuit structures having oxide sub-fins, are described. For example, an integrated circuit structure includes an oxide sub-fin structure having a top and sidewalls. An oxidation catalyst layer is on the top and sidewalls of the oxide sub-fin structure. A vertical arrangement of nanowires is above the oxide sub-fin structure. A gate stack is surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

Abstract: Gate-all-around integrated circuit structures having asymmetric source and drain contact structures, and methods of fabricating gate-all-around integrated circuit structures having asymmetric source and drain contact structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a fin. A gate stack is over the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. A first conductive contact structure is coupled to the first epitaxial source or drain structure. A second conductive contact structure is coupled to the second epitaxial source or drain structure. The second conductive contact structure is deeper along the fin than the first conductive contact structure.

Abstract: Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires.

Abstract: Gate-all-around integrated circuit structures having nanowires with tight vertical spacing, and methods of fabricating gate-all-around integrated circuit structures having nanowires with tight vertical spacing, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires. A vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers. A gate stack is around the vertical arrangement of horizontal silicon nanowires. A first source or drain structure is at a first end of the vertical arrangement of horizontal silicon nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal silicon nanowires.

Abstract: Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.

Abstract: Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

Abstract: Gate-all-around integrated circuit structures having oxide sub-fins, and methods of fabricating gate-all-around integrated circuit structures having oxide sub-fins, are described. For example, an integrated circuit structure includes an oxide sub-fin structure having a top and sidewalls. An oxidation catalyst layer is on the top and sidewalls of the oxide sub-fin structure. A vertical arrangement of nanowires is above the oxide sub-fin structure. A gate stack is surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.

Abstract: Self-aligned gate endcap architectures with gate-all-around devices having epitaxial source or drain structures are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. A gate endcap isolation structure is between the first and second gate stacks, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires and have an uppermost surface below an uppermost surface of the gate endcap isolation structure. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires and have an uppermost surface below the uppermost surface of the gate endcap isolation structure.

Abstract: A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

Abstract: Isolation schemes for gate-all-around (GAA) transistor devices are provided herein Integrated circuit structures including increased transistor source/drain contact area using a sacrificial source/drain layer are provided herein. In some cases, the isolation schemes include changing the semiconductor nanowires/nanoribbons in a targeted channel region between active or functional transistor devices to electrically isolate those active devices. The targeted channel region is referred to herein as a dummy channel region, as it is not used as an actual channel region for an active or functional transistor device. The semiconductor nanowires/nanoribbons in the dummy channel region can be changed by converting them to an electrical insulator and/or by adding dopant that is opposite in type relative to surrounding source/drain material (to create a p-n junction).

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to integrated circuits utilizing gate plugs to induce compressive channel strain. Other embodiments may be described or claimed.

Abstract: Integrated circuit structures having partitioned source or drain contact structures, and methods of fabricating integrated circuit structures having partitioned source or drain contact structures, are described. For example, an integrated circuit structure includes a fin. A gate stack is over the fin. A first epitaxial source or drain structure is at a first end of the fin. A second epitaxial source or drain structure is at a second end of the fin. A conductive contact structure is coupled to one of the first or the second epitaxial source or drain structures. The conductive contact structure has a first portion partitioned from a second portion.

Abstract: Methods, integrated circuit devices, and systems are discussed related to combining source and drain etch, cavity spacer formation, and source and drain semiconductor growth into a single lithographic processing step in gate-all-around transistors. Such combined processes are performed separately for NMOS and PMOS gate-all-around transistors by implementing selective masking techniques. The resulting transistor structures have improved cavity spacer integrity and contact to gate isolation.

Abstract: Fabrication techniques for NMOS and PMOS nanowires leveraging an isolated process flow for NMOS and PMOS nanowires facilitates independent (decoupled) tuning/variation of the respective geometries (i.e., sizing) and chemical composition of NMOS and PMOS nanowires existing in the same process. These independently tunable degrees of freedom are achieved due to fabrication techniques disclosed herein, which enable the ability to individually adjust the width of NMOS and PMOS nanowires as well as the general composition of the material forming these nanowires independently of one another.