Abstract: Disclosed herein are a method for forming bumps and a substrate including the bumps. The method includes: coating a solder resist on a substrate and electrodes formed on the substrate: performing laser etching treatment on the solder resist to form openings for forming bumps; printing a composition for forming bumps in the openings for forming bumps; and performing a reflowing process. The present invention can decrease the number of processes and realize a fine bump pitch of 90 ?m or less at the time of forming bumps. Further, the present invention can also decrease the number of times that alignment is performed, due to the decrease in the number of processes.

Abstract: Disclosed herein is a method for manufacturing a printed circuit board. The method for manufacturing a printed circuit board includes: preparing a base substrate having first connection pads and second connection pads; forming a solder resist layer on the base substrate, the solder resist layer having a first opening for exposing the first connection pads; forming a first surface treatment layer on the first connection pads; forming a protective film on the solder resist layer; forming a second opening for exposing the second connection pads in the protective film and the solder resist layer; and forming a second surface treatment layer on the second connection pads.

Abstract: Disclosed herein is a method for manufacturing a printed circuit board, including: forming a complex solder resist layer including a solder resist having an open part for forming a metal post and a cover film contacting the solder resist on a base substrate having an outer-layer circuit including a plating lead line; forming a metal post on the open part for forming the metal post by performing electroplating; removing the plating lead line; and exposing the metal post by removing the cover film.

Abstract: Disclosed herein are a printed circuit board including a first low-viscosity solder resist layer formed on one surface of a substrate having circuit patterns formed thereon and a second high-viscosity solder resist layer stacked on the first solder resist layer, thereby being advantageous in controlling the deviation in application thickness of solder resist (SR), while having excellent adhesion to the substrate, and a manufacturing method thereof.

Abstract: Disclosed herein are a substrate fabricating apparatus and a substrate fabricating method. The substrate fabricating apparatus includes: a first injector that injects a first etchant to a circuit layer formed as an outermost layer of a base substrate to form first type of ruggedness; and a second injector that injects a second etchant to the circuit layer formed with the first type of ruggedness to form second type of ruggedness. The present invention provides the substrate fabricating apparatus and the substrate fabricating method that inject different etchants to the circuit layer to form different ruggedness, thereby making it possible to widen the specific surface area of the circuit layer to improve adhesion between the circuit layer and the protective layer.

Abstract: Example embodiments relate to a semiconductor memory device and a system in which a plurality of semiconductor layers are stacked on each other. A 3-dimensional (3D) semiconductor memory device may include a plurality of semiconductor layers that are stacked on each other. The plurality of semiconductor layers may have the same memory cell structure. The 3D semiconductor memory device may include a first memory region including at least one semiconductor layer for storing system data and a second memory region including at least one semiconductor layer for storing data aside from the system data. The system data may include at least one piece of data selected from the group consisting of a booting code, a system code, and application software.

Abstract: A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

Abstract: Embodiments for performing clutter filtering in an ultrasound system are disclosed. In one embodiment, an ultrasound data acquisition unit acquires ultrasound data from a target object for color Doppler imaging and a processing unit extracts a plurality of frequency components of the ultrasound data using an autoregressive model and computes a mean frequency component of the plurality of frequency components. The processing unit detects frequency components corresponding to a clutter signal based on the plurality of frequency components and the mean frequency component and performs clutter filtering upon the ultrasound data by using the frequency components corresponding to the clutter signal.

Abstract: A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current.

Abstract: A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current.

Abstract: An exemplary content engine includes a content gateway configured to analyze and route content requests to a content server. The content server can be a cache server or a mobile content server. The cache server can be configured to receive and store cacheable web content from a controller that is configured to receive the cacheable web content from at least one cacheable web content provider, such as a web server, and route the content to the cache server. The mobile content server can be configured to receive, from the controller, and store the digital media content. The controller can be further configured to receive the digital media content from at least one external content server and route the content to the mobile content server. The content gateway can be further configured to receive non-cacheable web content from at least one non-cacheable web content provider.

Abstract: An exemplary content engine includes a content gateway configured to analyze and route content requests to a content server. The content server can be a cache server or a mobile content server. The cache server can be configured to receive and store cacheable web content from a controller that is configured to receive the cacheable web content from at least one cacheable web content provider, such as a web server, and route the content to the cache server. The mobile content server can be configured to receive, from the controller, and store the digital media content. The controller can be further configured to receive the digital media content from at least one external content server and route the content to the mobile content server. The content gateway can be further configured to receive non-cacheable web content from at least one non-cacheable web content provider.

Abstract: A system and method operable to monitor a parameter of a node of a communications network, enable one of a plurality of performance measurements for the node based on an enable threshold of the parameter and disable the one of the performance measurements based on a disable threshold of the parameter.

Abstract: A steel plate structure and a steel plate concrete wall are disclosed. A steel plate structure, which includes: a pair of steel plates, which are separated to provide a predetermined space; a structural member, which is positioned in the predetermined space, and which is structurally rigidly joined to one side of the steel plate in the direction of gravity; and a strut, which maintains a separation distance between the pair of steel plates, can be utilized to reduce the overall thickness of a steel plate concrete wall for efficient use of space, and to reduce the thickness of the steel plates for better welding properties and larger unit module sizes. Also, the axial forces or lateral forces applied on the steel plate concrete wall may be effectively resisted.

Abstract: A system for manufacturing a liquid crystal display includes a rotatable stage and a plurality of heads located on the rotatable stage. Each head is separated from each of its neighboring heads by a predetermined distance. The heads are enabled to rotate together with the rotatable stage in order to transport a tape carrier package (TCP). A first head retains the TCP and is located at a first position enabling the TCP to be detected. The first head is located at a second position enabling the first TCP to be pressed. The second position is different from the first position.

Abstract: A method of dynamic authentication configuration adjusts authentication configuration according to traffic patterns within a system, such as a cellular communications network. In a network, mobile devices are authenticated based on various events, such as an attach, location update, originated call, etc. According to a first embodiment, one or more authentication configuration profiles is defined for a VLR/SGSN and a time schedule/table to automatically update the authentication configurations based on a time. Accordingly, the number of authentications for a particular VLR is reduced as signaling traffic increases, and vice versa. In another exemplary embodiment, an HLR monitors system level traffic load to command each VLR and SGSN to change the authentication configurations. Authentication operations are preferably configured on per node and per traffic pattern basis.

Abstract: A memory device includes a decoder that sets an operational control signal and a column select line signal at a first logical level simultaneously. In addition, a local sense amplifier has at least one switching device that is turned on by the operational control signal that is at the first logical level to couple at least one local I/O line to at least one global I/O line. Furthermore, signal lines, that are disposed to be parallel, transmit the operational control signal and the column select line signal from the decoder.

Abstract: A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are possible. The semiconductor memory device may include an address bank buffer, address buffer, column predecoder and/or a decoder. The semiconductor memory device may begin execution of a write command in a bank in one clock cycle and begin execution of a read command in the following clock cycle, therefore, bus efficiency is increased and/or write-to-read turn around time is reduced.

Abstract: In one embodiment, a latency circuit generates the latency signal based on CAS latency information and read information. For example, the latency circuit may include a clock signal generating circuit generating a plurality of transfer signals and generating a plurality of sampling clock signals based on and corresponding to the plurality of transfer signals such that a timing relationship is created between the transfer signals and the sampling clock signals. The latency circuit may further include a latency signal generator selectively storing the read information based on the sampling clock signals, and selectively outputting the stored read information as the latency signal based on the transfer signals. The latency signal generator may also delay the read information such that the delayed, read information is stored based on the sampling clock signals.

Abstract: Methods of providing a delay for access to a memory device can include adjusting a delay for access to data during memory operations based on at least one parameter associated with a reduction in voltage levels provided to the memory. Related circuits are also disclosed.