Abstract: A memory device includes a decoder that sets an operational control signal and a column select line signal at a first logical level simultaneously. In addition, a local sense amplifier has at least one switching device that is turned on by the operational control signal that is at the first logical level to couple at least one local I/O line to at least one global I/O line. Furthermore, signal lines, that are disposed to be parallel, transmit the operational control signal and the column select line signal from the decoder.

Abstract: A method of measuring a frequency of an input clock signal may include generating an output pulse responsive to an edge of the input clock signal, and charging an electrical circuit responsive to the output pulse. An analog output signal may be generated responsive to the charged electrical circuit, and the analog output signal may be converted into a digital value representing a frequency of the input clock signal. Related frequency measuring circuits and memory devices are also discussed.

Abstract: A memory device includes a decoder that sets an operational control signal and a column select line signal at a first logical level simultaneously. In addition, a local sense amplifier has at least one switching device that is turned on by the operational control signal that is at the first logical level to couple at least one local I/O line to at least one global I/O line. Furthermore, signal lines, that are disposed to be parallel, transmit the operational control signal and the column select line signal from the decoder.

Abstract: A method of dynamic authentication configuration that adjust authentication configuration according to traffic patterns within a system, such as a cellular communications network. In a network, mobile devices are authenticated based on various events, such as an attach, location update, originated call, etc. According to a first embodiment, one or more authentication configuration profiles is defined for a VLR/SGSN and a time schedule/table to automatically update the authentication configurations based on a time. Accordingly, the number authentications for a particular VLR is reduced as signaling traffic increases, and vice versa. In another exemplary embodiment, an HLR monitors system level traffic load to command each VLR and SGSN to change the authentication configurations. Authentication operations are preferably configured on per node and per traffic pattern basis.

Abstract: Provided are a method of fabricating a stamp, a thin film transistor and a liquid crystal display device using the same. The stamp has an improved contact property with respect to a substrate. A charged zone is formed on the substrate using the stamp, and nano material charged with opposite charges to those of the charged zone is coated or plated to form a self-assembled monolayer (SAM). Therefore, the thin film transistor and the liquid crystal display device can have precise nano patterns, thereby improving the performance of the device.

Abstract: A frequency measuring circuit may include an edge detector, a charge pump, and an analog-to-digital (A/D) converter. The edge detector may be configured to generate an output pulse responsive to an edge of an input clock signal. The charge pump may be configured to generate an output signal responsive to the output pulse from the edge detector. The analog-to-digital (A/D) converter may be configured to convert the output signal into a digital value representing a frequency of the input clock signal. Related methods and integrated circuit memory devices are also discussed.

Abstract: A signal amplification circuit for a semiconductor memory device includes a current sense amplifier configured to receive a first signal pair and generate a second signal pair on a first pair of lines, an equalizer configured to equalize the first pair of lines, and a latch amplifier configured to generate a latch data output on a second pair of lines in response to the second signal pair.

Abstract: An oscillating force generator of an active vibration damper is provided that comprises in preferred aspects a housing in communication with a target object for which vibrations are to be reduced; an electromagnet; one or more permanent magnets; and inertial mass that can induce an inertial force. Preferred systems of the invention can generate a counter-oscillating force with relatively reduced power (current) input.

Abstract: A roll-fed system including a supply reel on which a continuum is wound, a cutter for separating a portion of the continuum from the continuum, a transferrer for transferring the continuum, and a plurality of supply controlling pulleys which are disposed between the cutter and a supply reel and move in opposed directions, wherein the continuum is alternately wound on each circumferential surface of the plurality of supply controlling pulleys and is transferred by the transferrer.

Abstract: A system for manufacturing a liquid crystal display includes a rotatable stage and a plurality of heads located on the rotatable stage. Each head is separated from each of its neighboring heads by a predetermined distance. The heads are enabled to rotate together with the rotatable stage in order to transport a tape carrier package (TCP). A first head retains the TCP and is located at a first position enabling the TCP to be detected. The first head is located at a second position enabling the first TCP to be pressed. The second position is different from the first position.

Abstract: The memory device includes a memory cell array, and an output buffer receiving data addressed from the memory cell array and outputting the data based on a latency signal. A latency circuit selectively associates at least one transfer signal with at least one sampling signal based on CAS latency information to create a desired timing relationship between the associated sampling and transfer signals. The latency circuit stores read information in accordance with at least one of the sampling signals, and generates a latency signal based on the transfer signal associated with the sampling signal used in storing the read information.

Abstract: A current sense amplifier includes first and second P type MOS transistors having source nodes connected to first and second sensing inputs, respectively, and gate and drain nodes being cross-coupled to each other. First and second N type MOS transistors have drain nodes connected to first and second sensing outputs, respectively, the first and second sensing outputs corresponding to the drain nodes of the first and second P type MOS transistors, respectively, the first and second N type MOS transistors having respective gate nodes connected to a power supply voltage. Third and fourth N type MOS transistors have drain nodes connected to the first and second sensing outputs, respectively, and gate nodes connected to a bias voltage node so that respective current paths are established from the first and second sensing outputs to a common reference node.

Abstract: An integrated online purchase reward system includes one or more first information processing devices, one or more second information processing devices, a network, and one or more purchase transaction monitoring devices which read in a purchase transaction medium, and print out purchase transaction records on the purchase transaction media as a hard copy. The first information processing devices receive, process, and distribute data, and respond to requests from the second information processing devices. The first information processing device includes database, and the second information processing devices are connected with the purchase transaction monitoring device. The network works on a TCP/IP Protocol environment and connects the first and the second information processing devices. The purchase transaction information including reward or gift is printed on a PET card through line thermal printing.

Abstract: In one embodiment, a latency circuit generates the latency signal based on CAS latency information and read information. For example, the latency circuit may include a clock signal generating circuit generating a plurality of transfer signals and generating a plurality of sampling clock signals based on and corresponding to the plurality of transfer signals such that a timing relationship is created between the transfer signals and the sampling clock signals. The latency circuit may further include a latency signal generator selectively storing the read information based on the sampling clock signals, and selectively outputting the stored read information as the latency signal based on the transfer signals. The latency signal generator may also delay the read information such that the delayed, read information is stored based on the sampling clock signals.

Abstract: A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current.

Abstract: A memory device includes a decoder that sets an operational control signal and a column select line signal at a first logical level simultaneously. In addition, a local sense amplifier has at least one switching device that is turned on by the operational control signal that is at the first logical level to couple at least one local I/O line to at least one global I/O line. Furthermore, signal lines, that are disposed to be parallel, transmit the operational control signal and the column select line signal from the decoder.

Abstract: The memory device includes a memory cell array, and an output buffer receiving data addressed from the memory cell array and outputting the data based on a latency signal. A latency circuit selectively associates at least one transfer signal with at least one sampling signal based on CAS latency information to create a desired timing relationship between the associated sampling and transfer signals. The latency circuit stores read information in accordance with at least one of the sampling signals, and generates a latency signal based on the transfer signal associated with the sampling signal used in storing the read information.

Abstract: The memory device includes a memory cell array, and an output buffer receiving data addressed from the memory cell array and outputting the data based on a latency signal. A latency circuit selectively associates at least one transfer signal with at least one sampling signal based on CAS latency information to create a desired timing relationship between the associated sampling and transfer signals. The latency circuit stores read information in accordance with at least one of the sampling signals, and generates a latency signal based on the transfer signal associated with the sampling signal used in storing the read information.

Abstract: A current sense amplifier includes first and second P type MOS transistors having source nodes connected to first and second sensing inputs, respectively, and gate and drain nodes being cross-coupled to each other. First and second N type MOS transistors have drain nodes connected to first and second sensing outputs, respectively, the first and second sensing outputs corresponding to the drain nodes of the first and second P type MOS transistors, respectively, the first and second N type MOS transistors having respective gate nodes connected to a power supply voltage. Third and fourth N type MOS transistors have drain nodes connected to the first and second sensing outputs, respectively, and gate nodes connected to a bias voltage node so that respective current paths are established from the first and second sensing outputs to a common reference node.

Abstract: A frequency measuring circuit may include an edge detector, a charge pump, and an analog-to-digital (A/D) converter. The edge detector may be configured to generate an output pulse responsive to an edge of an input clock signal. The charge pump may be configured to generate an output signal responsive to the output pulse from the edge detector. The analog-to-digital (A/D) converter may be configured to convert the output signal into a digital value representing a frequency of the input clock signal. Related methods and integrated circuit memory devices are also discussed.