Patents by Inventor Bo Rong
Bo Rong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240103097Abstract: The present disclosure provides a direct current (DC) transformer error detection apparatus for a pulsating harmonic signal, including a DC and pulsating harmonic current output module and an external detected input module, where the DC and pulsating harmonic current output module outputs a DC and a DC superimposed pulsating harmonic current to an internal sampling circuit and a self-calibrated standard resistor array; and the internal sampling circuit converts the input DC and the input DC superimposed pulsating harmonic current into a voltage signal, and sends the voltage signal to an analog-to-digital (AD) sampling and measurement component through a front-end conditioning circuit and a detected input channel. The DC transformer error detection apparatus can complete self-calibration for measurement of the DC and the pulsating harmonic signal on a test site.Type: ApplicationFiled: August 17, 2022Publication date: March 28, 2024Inventors: Xin Zheng, Wenjing Yu, Tao Peng, Yi Fang, Ming Lei, Hong Shi, Ben Ma, Li Ding, Wei Wei, Linghua Li, He Yu, Tian Xia, Yingchun Wang, Sike Wang, Dongri Xie, Xin Wang, Bo Pang, Xianjin Rong
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Publication number: 20240096781Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.Type: ApplicationFiled: March 20, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
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Patent number: 11935947Abstract: An enhancement mode high electron mobility transistor (HEMT) includes a group III-V semiconductor body, a group III-V barrier layer and a gate structure. The group III-V barrier layer is disposed on the group III-V semiconductor body, and the gate structure is a stacked structure disposed on the group III-V barrier layer. The gate structure includes a gate dielectric and a group III-V gate layer disposed on the gate dielectric, and the thickness of the gate dielectric is between 15 nm to 25 nm.Type: GrantFiled: October 8, 2019Date of Patent: March 19, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Shin-Chuan Huang, Wen-Jung Liao, Chun-Liang Hou
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Publication number: 20240080173Abstract: An electronic device includes a processor circuit, a frequency-domain-to-time-domain conversion circuit, a transmitter circuit, a hybrid circuit, a receiver circuit, and a time-domain-to-frequency-domain conversion circuit. The processor circuit generates a frequency-domain transmitting signal. The frequency-domain-to-time-domain conversion circuit converts the frequency-domain transmitting signal into a first time-domain transmitting signal. The transmitter circuit generates a second time-domain transmitting signal. The hybrid circuit includes an echo noise cancelling path and an echo noise path. When the echo noise cancelling path is turned off, the processor circuit receives a first frequency-domain receiving signal. When the echo noise cancelling path is turned on, the processor circuit receives a second frequency-domain receiving signal.Type: ApplicationFiled: June 27, 2023Publication date: March 7, 2024Inventors: Cheng-Hsien LI, Bo-Rong HUANG
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Patent number: 11914887Abstract: A storage device and a data accessing method are disclosed, wherein the storage device includes a memory circuit and a control circuit. The memory circuit includes a plurality of multi-level cells, and each of the multi-level cells is configured to store at least a first bit, a second bit and a third bit in at least a first page, a second page and a third page. The control circuit is configured to read the first bits according to a one-time reading operation related to the first bits, read the second bits according to M-times reading operations related to the second bits, and read the third bits according to N-times reading operations related to the third bits, wherein the difference between M and N is less than or equal to one.Type: GrantFiled: August 17, 2021Date of Patent: February 27, 2024Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yung-Chun Li, Han-Wen Hu, Bo-Rong Lin, Huai-Mu Wang
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Publication number: 20240064952Abstract: A semiconductor memory device includes a first dielectric wall, a second dielectric wall, first channel portions, second channel portions, an isolation wall, and a dielectric feature. The second dielectric wall is spaced apart from the first dielectric wall in a first direction. The first channel portions are disposed on a side of the first dielectric wall and are spaced apart from each other in a second direction transverse to the first direction. The second channel portions are disposed on a side of the second dielectric wall and are spaced apart from each other in the second direction. The isolation wall is located between the first dielectric wall and the second dielectric wall. The dielectric feature is disposed to separate the first dielectric wall and the isolation wall, and is disposed on the other side of the first dielectric wall opposite to the first channel portions in the first direction.Type: ApplicationFiled: August 22, 2022Publication date: February 22, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bo-Rong LIN, Kuo-Cheng CHIANG, Shi-Ning JU, Guan-Lin CHEN, Chih-Hao WANG
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Publication number: 20240063065Abstract: A method for forming a semiconductor structure is provided. The method includes forming first, second and third fin structures over a substrate, forming a first dielectric material along a first trench between the first fin structure and the second fin structure and along a second trench between the second fin structure and the third fin structure, removing a first portion of the first dielectric material along the second trench while leaving a second portion of the first dielectric material along the first trench as a dielectric liner, depositing a second dielectric material over the dielectric liner and filling the first trench and the second trench, and etching back the second dielectric material until the dielectric liner is exposed. A first portion of the second dielectric material remaining in the first trench forms a dielectric wall.Type: ApplicationFiled: August 17, 2022Publication date: February 22, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bo-Rong LIN, Kuo-Cheng CHIANG, Shi-Ning JU, Guan-Lin CHEN, Chih-Hao WANG
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Patent number: 11873605Abstract: The present invention relates to a liquid-state temporary reinforcing material, a preparation method therefor and an application thereof. The liquid-state temporary reinforcing material comprises a reinforcing material and a crystallization inhibitor; the reinforcing material is selected from molecules of any two or more of menthol, menthone, menthol ester and menthol ether, and the content of the crystallization inhibitor is less than 50 ppm. For the liquid-state temporary reinforcing material of the present invention, the menthol and the derivatives of the liquid-state temporary reinforcing material are integrally mixed together to form the composite material for temporary reinforcing, the composite material being liquid and volatilization-controllable at room temperature. Thus, the temporary reinforcing requirements for extracting cultural relics at an archaeology excavation site may be met, and the material is convenient to use.Type: GrantFiled: June 15, 2018Date of Patent: January 16, 2024Assignee: SHANGHAI UNIVERSITYInventors: Hongjie Luo, Xiao Huang, Yarong Yu, Xiangna Han, Bo Rong, Qinghua Ren
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Publication number: 20240014310Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.Type: ApplicationFiled: September 21, 2023Publication date: January 11, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shin-Chuan Huang, Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
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Patent number: 11868839Abstract: A device detecting system is provided. The device detecting system includes a bar code scanner, a plurality of device accommodating spaces, a screen, and a server. The server obtains bar code information via the bar code scanner and opens one of the device accommodating spaces based on the bar code information to accommodate an electronic device. The server performs a test procedure on the electronic device to generate a test result, and displays the test result and operation information corresponding to the test result on the screen.Type: GrantFiled: May 5, 2022Date of Patent: January 9, 2024Assignee: ASUSTEK COMPUTER INC.Inventors: Chien-Chih Chang, Pei-Yin Chen, Wei-Han Lin, Bo-Rong Chu, Yen-Ting Liu, Yu-Shen Mai, Kuan-Yu Hsiao, Chia-Hsien Lin, Pei-Yu Liao, Chun-Yen Lai, Sheng-Yi Chen
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Publication number: 20230378314Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.Type: ApplicationFiled: July 13, 2023Publication date: November 23, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Bo-Rong Chen, Che-Hung Huang, Chun-Ming Chang, Yi-Shan Hsu, Chih-Tung Yeh, Shin-Chuan Huang, Wen-Jung Liao, Chun-Liang Hou
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Publication number: 20230369448Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.Type: ApplicationFiled: July 13, 2023Publication date: November 16, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Bo-Rong Chen, Che-Hung Huang, Chun-Ming Chang, Yi-Shan Hsu, Chih-Tung Yeh, Shin-Chuan Huang, Wen-Jung Liao, Chun-Liang Hou
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Patent number: 11809838Abstract: A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit coupled to the memory array, for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results; a counting unit coupled to the multiplication circuit, for performing bitwise counting on the multiplication results to generate a MAC (multiplication and accumulation) operation result.Type: GrantFiled: July 1, 2021Date of Patent: November 7, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Han-Wen Hu, Yung-Chun Lee, Bo-Rong Lin, Huai-Mu Wang
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Patent number: 11804544Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.Type: GrantFiled: January 14, 2022Date of Patent: October 31, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shin-Chuan Huang, Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
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Patent number: 11749740Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.Type: GrantFiled: December 31, 2019Date of Patent: September 5, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Bo-Rong Chen, Che-Hung Huang, Chun-Ming Chang, Yi-Shan Hsu, Chih-Tung Yeh, Shin-Chuan Huang, Wen-Jung Liao, Chun-Liang Hou
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Patent number: 11704246Abstract: A memory system for maintaining data consistency and an operation method thereof are provided. The operation method includes: receiving a first data in a first cache of a first memory from a processor; reading the first data from the first cache and writing the first data as a redo log into a log buffer of the first memory; writing the redo log from the log buffer into a memory controller of the processor; performing an in-memory copy in a second memory to copy a second data as an undo log, wherein the second data is an old version of the first data; and writing the redo log from the memory controller into the second memory for covering the second data by the redo log as a third data, wherein the redo log, the third data and the first data are the same.Type: GrantFiled: December 1, 2021Date of Patent: July 18, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Bo-Rong Lin, Ming-Liang Wei, Hsiang-Pang Li, Nai-Jia Dong, Hsiang-Yun Cheng, Chia-Lin Yang
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Patent number: 11656988Abstract: A memory device and an operation method thereof are provided. The memory device includes: a plurality of page buffers, storing an input data; a plurality of memory planes coupled to the page buffers, based on received addresses of the memory planes, a plurality of weights stored in the memory planes, the memory planes performing bit multiplication on the weights and the input data in the page buffers in parallel to generate a plurality of bit multiplication results in parallel, the bit multiplication results stored back to the page buffers; and at least one accumulation circuit coupled to the page buffers, for performing bit accumulation on the bit multiplication results of the memory planes in parallel or in sequential to generate a multiply-accumulate (MAC) operation result.Type: GrantFiled: December 6, 2021Date of Patent: May 23, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Han-Wen Hu, Yung-Chun Li, Bo-Rong Lin, Huai-Mu Wang
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Patent number: D989485Type: GrantFiled: April 27, 2021Date of Patent: June 20, 2023Assignee: DONGGUAN EDIFIER TECHNOLOGY CO., LTD.Inventor: Bo Rong
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Patent number: D993940Type: GrantFiled: August 29, 2021Date of Patent: August 1, 2023Assignee: Dongguan Edifier Technology Co., Ltd.Inventor: Bo Rong
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Patent number: D996358Type: GrantFiled: July 6, 2022Date of Patent: August 22, 2023Assignee: BEIJING EDIFIER TECHNOLOGY CO., LTDInventor: Bo Rong