Patents by Inventor Bo Zheng

Bo Zheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • BIG DATA SOURCING SIMULATOR
    Publication number: 20160110681
    Abstract: A simulator is configured to simulate the fulfillment of orders by nodes. Each node has an inventory of products and is capable of shipping the products to destinations in response to receipt of a corresponding order. The simulator divides the nodes into groups and assigns a different priority to each group based on input provided by a user to the simulator to generate an ordered sequence of priorities. The simulator maintains safety stock data corresponding to each node that indicates minimum quantities of the products required to be present at the corresponding node. The simulator selects a current priority of the sequence and next simulates a first group among the groups having the current priority fulfilling the orders for a given product among the products while a quantity of the given product at each of the nodes in the first group is below the minimum quantity in the corresponding safety stock data.
    Type: Application
    Filed: October 13, 2015
    Publication date: April 21, 2016
    Inventors: JoAnn Piersa Brereton, Ajay Ashok Deshpande, Arun Hampapur, Miao He, Alan Jonathan King, Xuan Liu, Christopher Scott Milite, Jae-Eun Park, Joline Ann Villaranda Uichanco, Songhua Xing, Steven lgrejas, Hongliang Fei, Vadiraja Ramamurthy, Yingjie Li, Kimberly D. Hendrix, Xiao Bo Zheng
  • BIG DATA SOURCING SIMULATOR
    Publication number: 20160110735
    Abstract: A simulator is configured to simulate the fulfillment of orders by nodes. Each node has an inventory of products and is capable of shipping the products to destinations in response to receipt of a corresponding order. The simulator divides the nodes into groups and assigns a different priority to each group based on input provided by a user to the simulator to generate an ordered sequence of priorities. The simulator maintains safety stock data corresponding to each node that indicates minimum quantities of the products required to be present at the corresponding node. The simulator selects a current priority of the sequence and next simulates a first group among the groups having the current priority fulfilling the orders for a given product among the products while a quantity of the given product at each of the nodes in the first group is below the minimum quantity in the corresponding safety stock data.
    Type: Application
    Filed: December 1, 2015
    Publication date: April 21, 2016
    Inventors: JoAnn Piersa Brereton, Ajay Ashok Deshpande, Arun Hampapur, Miao He, Alan Jonathan King, Xuan Liu, Christopher Scott Milite, Jae-Eun Park, Joline Ann Villaranda Uichanco, Songhua Xing, Steve Igrejas, Hongliang Fei, Vadiraja Ramamurthy, Yingjie Li, Kimberly D. Hendrix, Xiao Bo Zheng
  • PRE-CLEAN OF SILICON GERMANIUM FOR PRE-METAL CONTACT AT SOURCE AND DRAIN AND PRE-HIGH K AT CHANNEL
    Publication number: 20160079062
    Abstract: The present disclosure generally relates to methods for removing contaminants and native oxides from substrate surfaces. The method includes exposing a surface of the substrate to first hydrogen radical species, wherein the substrate is silicon germanium having a concentration of germanium above about 30%, then exposing the surface of the substrate to a plasma formed from a fluorine-containing precursor and a hydrogen-containing precursor, and then exposing the surface of the substrate to second hydrogen radical species.
    Type: Application
    Filed: September 4, 2015
    Publication date: March 17, 2016
    Inventors: Bo ZHENG, Avgerinos V. GELATOS, Anshul VYAS, Raymond Hoiman HUNG
  • Automatic proxy device configuration
    Patent number: 9264432
    Abstract: A traffic management device (TMD), system, and processor-readable storage medium directed towards automatically configuring an AAA proxy device (also referred to herein as “the proxy”) to load-balance AAA request messages across a plurality of AAA server devices. In one embodiment the proxy receives an AAA handshake message from an AAA client device. The proxy forwards the handshake message to each of the plurality of server devices and, in reply, receives an AAA handshake response message from each of the plurality of server devices. The proxy extracts attributes from each of the handshake response messages and automatically configures itself based on the extracted attributes. The proxy then load-balances, modifies and/or routes subsequently received AAA request messages based on the extracted attributes.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: February 16, 2016
    Assignee: F5 Networks, Inc.
    Inventors: Tao Liu, Song Bo Zheng
  • Memory Circuitry Using Write Assist Voltage Boost
    Publication number: 20160005448
    Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.
    Type: Application
    Filed: September 17, 2015
    Publication date: January 7, 2016
    Inventors: Andy Wangkun Chen, Yew Keong Chong, Gus Yeung, Bo Zheng, George Lattimore
  • Integrated platform for fabricating n-type metal oxide semiconductor (NMOS) devices
    Patent number: 9230835
    Abstract: Embodiments of an integrated platform for fabricating n-type metal oxide semiconductor (NMOS) devices are provided herein. In some embodiments, an integrated platform for fabricating n-type metal oxide semiconductor (NMOS) devices may include a first deposition chamber configured to deposit a first layer atop the substrate, the first layer comprising titanium oxide (TiO2) or selenium (Se); a second deposition chamber configured to deposit a second layer atop the first layer, the second layer comprising titanium; a third deposition chamber configured to deposit a third layer atop the second layer, the third layer comprising one of titanium nitride (TiN) or tungsten nitride (WN).
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: January 5, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Avgerinos V. Gelatos, Srinivas Gandikota, Seshadri Ganguli, Xinyu Fu, Bo Zheng, Yu Lei
  • Memory device and method of controlling leakage current within such a memory device
    Patent number: 9171634
    Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column has an active mode of operation where a read operation may be performed on an activated memory cell within that column group, and a non-active mode of operation where the read operation is not performable. Precharge circuitry is used, for each column group, to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell includes coupling circuitry connected between the associated read bit line and a reference line associated with the column group containing that memory cell.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 27, 2015
    Assignee: ARM Limited
    Inventors: Bo Zheng, Gus Yeung, Fakhruddin ali Bohra
  • Memory circuitry using write assist voltage boost
    Patent number: 9142266
    Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: September 22, 2015
    Assignee: ARM Limited
    Inventors: Andy Wangkun Chen, Yew Keong Chong, Gus Yeung, Bo Zheng, George Lattimore
  • Film Deposition Using Spatial Atomic Layer Deposition Or Pulsed Chemical Vapor Deposition
    Publication number: 20150194298
    Abstract: Provided are atomic layer deposition methods to deposit a film using a circular batch processing chamber with a plurality of sections separated by gas curtains so that each section independently has a process condition.
    Type: Application
    Filed: December 31, 2014
    Publication date: July 9, 2015
    Inventors: Yu Lei, Srinivas Gandikota, Seshadri Ganguli, Bo Zheng, Rajkumar Jakkaraju, Martin Jeff Salinas, Benjamin Schmiege
  • Integrated level shifting latch circuit and method of operation of such a latch circuit
    Patent number: 9069652
    Abstract: An integrated level shifting latch circuit receives an input signal in a first voltage domain and generates an output signal in a second voltage domain. Data retention circuitry operates in a transparent phase where a data value is subjected to a level shifting function and is written into the data retention circuitry dependent on the input signal. Control circuitry controls the data retention circuitry to operate in the transparent phase during a first phase of the clock signal and to operate in the latching phase during a second phase of the clock signal. Writing circuitry writes the data value into the data retention circuitry. Contention mitigation circuitry, during the transparent phase, reduces a voltage drop across at least one component within the data retention circuitry.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: June 30, 2015
    Assignee: ARM Limited
    Inventors: Gus Yeung, Bo Zheng, Frank Guo
  • Memory circuitry with write assist
    Patent number: 9070431
    Abstract: Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: June 30, 2015
    Assignee: ARM Limited
    Inventors: Frank Guo, Martin Jay Kinkade, Bo Zheng, Brian Reed, Shrisagar Dwivedi
  • MEMORY CIRCUITRY USING WRITE ASSIST VOLTAGE BOOST
    Publication number: 20150138901
    Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 21, 2015
    Applicant: ARM LIMITED
    Inventors: Andy Wangkun CHEN, Yew Keong Chong, Gus Yeung, Bo Zheng, George Lattimore
  • MEMORY CIRCUITRY WITH WRITE ASSIST
    Publication number: 20150117119
    Abstract: Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage.
    Type: Application
    Filed: October 25, 2013
    Publication date: April 30, 2015
    Applicant: ARM LIMITED
    Inventors: Frank GUO, Martin Jay Kinkade, Bo Zheng, Brian Reed, Shrisagar Dwivedi
  • Apparatuses and methods for atomic layer deposition
    Patent number: 9017776
    Abstract: Embodiments of the invention provide apparatuses and methods for atomic layer deposition (ALD), such as plasma-enhanced ALD (PE-ALD). In some embodiments, a PE-ALD chamber is provided which includes a chamber lid assembly coupled with a chamber body having a substrate support therein. In one embodiment, the chamber lid assembly has an inlet manifold assembly containing an annular channel encompassing a centralized channel, wherein the centralized channel extends through the inlet manifold assembly, and the inlet manifold assembly further contains injection holes extending from the annular channel, through a sidewall of the centralized channel, and to the centralized channel.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: April 28, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Hyman W. H. Lam, Bo Zheng, Hua Ai, Michael Jackson, Xiaoxiong Yuan, Hou Gong Wang, Salvador P. Umotoy, Sang Ho Yu
  • METHOD OF ENABLING SEAMLESS COBALT GAP-FILL
    Publication number: 20150093891
    Abstract: Methods for depositing a metal layer in a feature definition of a semiconductor device are provided. In one implementation, a method for depositing a metal layer for forming a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a metal layer on a substrate and annealing the metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the metal layer on the substrate, exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process until a predetermined thickness of the metal layer is achieved.
    Type: Application
    Filed: September 10, 2014
    Publication date: April 2, 2015
    Inventors: Bhushan N. ZOPE, Avgerinos V. GELATOS, Bo ZHENG, Yu LEI, Xinyu FU, Srinivas GANDIKOTA, Sang Ho YU, Mathew ABRAHAM
  • MEMORY DEVICE AND METHOD OF OPERATION OF SUCH A MEMORY DEVICE
    Publication number: 20150085586
    Abstract: A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 26, 2015
    Applicant: ARM LIMITED
    Inventors: Bo ZHENG, Jungtae KWON, Gus YEUNG, Yew Keong CHONG
  • Memory device and method of operation of such a memory device
    Patent number: 8971133
    Abstract: A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: March 3, 2015
    Assignee: ARM Limited
    Inventors: Bo Zheng, Jungtae Kwon, Gus Yeung, Yew Keong Chong
  • Method for removing native oxide and associated residue from a substrate
    Patent number: 8951913
    Abstract: Native oxides and associated residue are removed from surfaces of a substrate by sequentially performing two plasma cleaning processes on the substrate in a single processing chamber. The first plasma cleaning process removes native oxide formed on a substrate surface by generating a cleaning plasma from a mixture of ammonia (NH3) and nitrogen trifluoride (NF3) gases, condensing products of the cleaning plasma on the native oxide to form a thin film that contains ammonium hexafluorosilicate ((NH4)2SiF6), and subliming the thin film off of the substrate surface. The second plasma cleaning process removes remaining residues of the thin film by generating a second cleaning plasma from nitrogen trifluoride gas. Products of the second cleaning plasma react with a few angstroms of the bare silicon present on the surface, forming silicon tetrafluoride (SiF4) and lifting off residues of the thin film.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: February 10, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Bo Zheng, Arvind Sundarrajan, Xinyu Fu
  • MICROARRAY SUBSTRATE, MICROARRAY, MICROFLUIDIC SYSTEM AND METHODS FOR PREPARING THE SAME
    Publication number: 20150038364
    Abstract: A microarray substrate including a piece of fluoropolymer whose surface is modified with polydopamine, in which the polydopamine forms an array of microspots on the surface of the fluoropolymer piece, and allows immobilization of molecules or cells. A microarray including the substrate, a microfluidic system designed for dispensing reagents onto selected locations on the surface of substrates, and a method for preparing the substrate and the microarray, in which a dopamine solution is dispensed onto the fluoropolymer piece using the microfluidic system, and forms an array of polydopamine microspots serving as the reaction sites for microarray analysis.
    Type: Application
    Filed: July 29, 2014
    Publication date: February 5, 2015
    Inventors: Bo Zheng, Hui Feng
  • COBALT SUBSTRATE PROCESSING SYSTEMS, APPARATUS, AND METHODS
    Publication number: 20150030771
    Abstract: Electronic device processing systems including cobalt deposition are described. One system includes a mainframe having a transfer chamber and at least two facets, and one or more process chambers adapted to carry out a metal reduction or metal oxide reduction process and possibly an annealing processes on substrates, and one or more deposition process chambers adapted to carry out a cobalt deposition process. Other systems includes a transfer chamber, one or more load lock process chambers coupled to the transfer chamber that are adapted to carry out a metal reduction or metal oxide reduction process. Additional methods and systems for cobalt deposition processing of substrates are described, as are numerous other aspects.
    Type: Application
    Filed: July 22, 2014
    Publication date: January 29, 2015
    Inventors: Avgerinos V. Gelatos, Bhushan Zope, Bo Zheng