Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

Abstract: The invention relates to a resonator circuit, the resonator circuit comprising a transformer comprising a primary winding and a secondary winding, wherein the primary winding is inductively coupled with the secondary winding, a primary capacitor being connected to the primary winding, the primary capacitor and the primary winding forming a primary circuit, and a secondary capacitor being connected to the secondary winding, the secondary capacitor and the secondary winding forming a secondary circuit, wherein the resonator circuit has a common mode resonance frequency at an excitation of the primary circuit in a common mode, wherein the resonator circuit has a differential mode resonance frequency at an excitation of the primary circuit in a differential mode, and wherein the common mode resonance frequency is different from the differential mode resonance frequency.

Abstract: A novel and useful transmitter (TX) architecture for ultra-low power (ULP) radios. An all-digital PLL employs a digitally controlled oscillator (DCO) having switching current sources to reduce supply voltage and power consumption without sacrificing phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL after settling to reduce its sampling rate or shut it off entirely during direct DCO data modulation. A switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency. The transmitter has been realized in 28 nm CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy.

Abstract: A time-to-digital converter includes: an input for receiving a time-domain input signal; an output for providing a digital output signal; a time register coupled to the input and to a first node; a time quantizer coupled to the time register for providing the digital output signal at the output; and a digital-to-time converter coupled to the output for providing a feed-back signal at the first node.

Abstract: A time register includes: a pair of inputs coupled to a pair of input clocks; a pair of tri-state inverters for producing a pair of level signals; and a pair of outputs coupled to the level signals for producing a pair of output clocks, wherein the tri-state inverters are responsive to a pair of state signals and the pair of input clocks for holding or discharging the level signals.

Abstract: The embodiments of the invention relate to a radio frequency oscillator, the radio frequency oscillator comprising a resonator circuit resonant at an excitation of the resonator circuit in a differential mode and at an excitation of the resonator circuit in a common mode, wherein the resonator circuit has a differential mode resonance frequency at the excitation in the differential mode, and wherein the resonator circuit has a common mode resonance frequency at the excitation in the common mode, a first excitation circuit configured to excite the resonator circuit in the differential mode to obtain a differential mode oscillator signal oscillating at the differential mode resonance frequency, and a second excitation circuit configured to excite the resonator circuit in the common mode to obtain a common mode oscillator signal oscillating at the common mode resonance frequency.

Abstract: A transformer includes: a primary winding comprising a first port, a second port and a metal layer connected between the first port and the second port, the metal layer comprising a plurality of sections of different electrical lengths and/or characteristic impedances; and a secondary winding electromagnetically coupled with the primary winding, the secondary winding comprising a first port, a second port and a metal layer connected between the first port and the second port, the metal layer comprising a plurality of sections of different electrical lengths and/or characteristic impedances.

Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

Abstract: A novel and useful transmitter (TX) architecture for ultra-low power (ULP) radios. An all-digital PLL employs a digitally controlled oscillator (DCO) having switching current sources to reduce supply voltage and power consumption without sacrificing phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL after settling to reduce its sampling rate or shut it off entirely during direct DCO data modulation. A switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency. The transmitter has been realized in 28 nm CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy.

Abstract: A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.

Abstract: The present disclosure relates to a method for demodulating a modulated signal and a receiver. The receiver comprises: a phase detector with a first and second input, the first input being adapted to receive a modulated input signal; a comparator comprising an input coupled to an output of the phase detector; a frequency-offset cancellation block comprising an input coupled to an output of the comparator. The receiver includes a digitally controlled oscillator comprising: a control input coupled to an output of the comparator and an output of the frequency-offset cancellation block; and an output coupled to the second input of the phase detector.

Abstract: A novel and useful transmitter (TX) architecture for ultra-low power (ULP) radios. An all-digital PLL employs a digitally controlled oscillator (DCO) having switching current sources to reduce supply voltage and power consumption without sacrificing phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL after settling to reduce its sampling rate or shut it off entirely during direct DCO data modulation. A switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency. The transmitter has been realized in 28 nm CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy.

Abstract: A charge sharing filter includes a rotating capacitor, and a plurality of elementary filters, each elementary filter comprising: an elementary switch coupled between a first node of the respective elementary filter and a second node of the respective elementary filter; and a history capacitor coupled to the first node of the respective elementary filter, wherein the second nodes of the plurality of elementary filters are interconnected with the rotating capacitor in one interconnecting node.

Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

Abstract: A calibration procedure that uses direct measurement of digital phase error performance for low cost calibration of all-digital phase locked loop (ADPLL)/digitally-controlled oscillator (DCO) is described. Direct measurement of digital phase error, or difference in digital phase error, is used to adjust the operating point of the DCO and thereby determine the operating point that provides the optimal phase noise of the output signal. Calibration may be performed at any time so that changes in external factors such as process, voltage and temperature (PVT) may be incorporated into the setting of the operating point of the DCO.

Abstract: A quadrature LC tank based digitally controlled ring oscillator (DCO). The oscillator structure incorporates a plurality of stages, each stage including a buffer and a series LC tank. Four stages are coupled together to create a 360 degree phase shift around a loop. The oscillation frequency of the oscillator is the same as the resonant frequency of each LC tank, therefore it avoids quality factor degradation of LC tanks found in the prior art. In one example embodiment, class-D amplifiers are used to drive each of the LC tanks. Capacitor banks before at the input and output of the buffers provide coarse and fine tuning of the frequency of oscillation. The high efficiency exhibited by these amplifiers results in very good phase noise performance of this oscillator. The oscillator utilizes a startup circuit to launch oscillation upon power on.

Abstract: A novel and useful fully integrated switched-mode wideband 60 GHz power amplifier architecture. Using an appropriate second-harmonic termination of its output matching network, the required systematic peak current of the final stage is reduced such that the PA functions as a class-E/F2 switched-mode PA at saturation. In addition, low/moderate magnetic coupling factor transformers in the intermediate stages enable the PA to reach a high power added efficiency (PAE) and bandwidth product. Transformers of low/moderate coupling are also utilized in the preliminary stages of the PA to improve the overall bandwidth. In addition, the PA exploits the different behavior of the output impedance matching network for differential mode (DM) and common mode (CM) excitations. The PA is also stabilized against the combination of DM and CM oscillation modes. The PA also provides a technique to stabilize transformer-based mm-wave amplifiers against various modes of undesired oscillations.

Abstract: A quadrature LC tank based digitally controlled ring oscillator (DCO). The oscillator structure incorporates a plurality of stages, each stage including a buffer and a series LC tank. Four stages are coupled together to create a 360 degree phase shift around a loop. The oscillation frequency of the oscillator is the same as the resonant frequency of each LC tank, therefore it avoids quality factor degradation of LC tanks found in the prior art. In one example embodiment, class-D amplifiers are used to drive each of the LC tanks. Capacitor banks before at the input and output of the buffers provide coarse and fine tuning of the frequency of oscillation. The high efficiency exhibited by these amplifiers results in very good phase noise performance of this oscillator. The oscillator utilizes a startup circuit to launch oscillation upon power on.

Abstract: A calibration procedure that uses direct measurement of digital phase error performance for low cost calibration of all-digital phase locked loop (ADPLL)/digitally-controlled oscillator (DCO) is described. Direct measurement of digital phase error, or difference in digital phase error, is used to adjust the operating point of the DCO and thereby determine the operating point that provides the optimal phase noise of the output signal. Calibration may be performed at any time so that changes in external factors such as process, voltage and temperature (PVT) may be incorporated into the setting of the operating point of the DCO.

Abstract: A radio frequency (RF) signal can be produced with an RF frequency that is responsive to a frequency reference (FREF) clock. An inductive-capacitive (LC) tank oscillator circuit can generate the RF signal. A digital to time converter (DTC) circuit can operate, for a first edge of the FREF clock, in a baseline mode that has a first delay, and for a subsequent edge of the FREF clock, in a delay mode that introduces a second delay value to the FREF clock. A controller circuit can enable the LC-tank oscillator circuit in response to a first edge of the FREF clock and to set or increase the second delay value of the delay mode as a function of the frequency of the RF signal. A phase detector circuit can detect, for the subsequent edge of the FREF clock, a phase difference between the FREF clock and the RF signal.