Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a first device and a second device coupled to a surface of a substrate, and a continuous flexible shield woven over the first device and under the second device to separate the first device from the second device. In selected examples, the continuous flexible shield may be formed from a laminate and one or more of the devices may be coupled through an opening or via in the continuous flexible shield.

Abstract: An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.

Abstract: According to various examples, a device is described. The device may include a first package substrate. The device may also include a first mold layer with a first thickness. The device may also include a second mold layer with a second thickness proximal to the first mold layer. The second thickness may be larger than the first thickness. The first mold layer may include a plurality of first interconnects coupled to the first package substrate. The second mold layer may include a plurality of second interconnects configured to couple the first package substrate to a printed circuit board.

Abstract: The present disclosure relates to a semiconductor package that may include a package substrate with a first surface and an opposing second surface, a first device coupled to the first surface of the package substrate, a redistribution frame coupled to the second surface of the package substrate, a plurality of solder balls coupled to the second surface of the package substrate, a second device coupled to the redistribution frame, and a printed circuit board coupled to the plurality of solder balls on the second surface of substrate, wherein the redistribution frame coupled with the second device and the plurality of solder balls are positioned between the package substrate and the printed circuit board.

Abstract: Techniques and mechanisms for mitigating the effect of signal noise on communication via an interconnect. In an embodiment, a substrate includes an interconnect and a conductor which has a hole formed therein. Portions of the interconnect variously extend over a side of the conductor, wherein another recess portion of the interconnect extends from a plane which includes the side, and further extends at least partially into the hole. The configuration of the recess portion extending within the hole may contribute to an impedance which dampens a transmitter slew rate of the communication. In an embodiment, a total distance along a path formed by the interconnect is equal to or less than 5.5 inches.

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

Abstract: A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture.

Abstract: A semiconductor package substrate includes an encapsulated interconnect on a land side of the substrate. The encapsulated interconnect includes an integral metallic structure that has a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting.

Abstract: A semiconductor package substrate includes an encapsulated interconnect on a land side of the substrate. The encapsulated interconnect includes an integral metallic structure that has a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include a semiconductor package including a package substrate, a first semiconductor die on the package substrate, a second semiconductor die on the package substrate, a third semiconductor die on the package substrate, and a bridge interconnect at least partially embedded in the package substrate. The bridge interconnect can include a first bridge section coupling the first semiconductor die to the second semiconductor die, a second bridge section coupling the second semiconductor die to the third semiconductor die, and a power-ground section between the first section and the second section, the power-ground section comprising first and second conductive traces coupled to the second semiconductor die.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a semiconductor article having a package substrate, a first semiconductor die coupled to the package substrate, a second semiconductor die coupled to the package substrate and adjacent the first semiconductor die, and a bridge component therebetween coupling the first semiconductor die to the second semiconductor die. The bridge component can include a bridge substrate, a conductive trace therein, and a passive component coupled to the conductive trace.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include an assembly having asymmetrically situated conductors. In selected examples, the assembly includes a ground plane, a central shield portion, a first side shield portion on a. first side, a second side shield portion on a second side, a first conductor asymmetrically situated between the central shield portion and the first side shield portion, a second conductor asymmetrically situated between the central shield portion and the second side shield portion, and dielectric within the assembly.

Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a substrate, a semiconductor die thereon, electrically coupled to the substrate, and an interposer adapted to connect the substrate to a circuit board. The interposer can include a major surface, a recess in the major surface, a first plurality of interconnects passing through the interposer within the recess to electrically couple the substrate to a circuit board, and a second plurality of interconnects on the major surface of the interposer to electrically couple the substrate to the circuit board, wherein each of the second plurality of interconnects comprises a smaller cross-section than some of the first plurality of interconnects.

Abstract: Disclosed embodiments include multi-level fan-out integrated-circuit package substrates that provide a low-loss path to active and passive devices, by shunting away from interconnects and inductive loops. The multi-level form factor of a molded mass, allows for the low-loss path.

Abstract: An electronic device comprises an integrated circuit (IC) die including a first plurality of contact pads; and a plurality of stacked interconnect layers. The plurality of stacked interconnect layer include a first interconnect layer including a first conductive plane, a first vertical interconnect portion, and dielectric material isolating the first vertical interconnect portion from the first conductive plane; and a second interconnect layer including a second conductive plane contacting the first conductive plane, a second vertical interconnect portion contacting the first vertical interconnect portion, and the dielectric material isolating the second vertical interconnect portion from the second conductive plane; wherein the first and second vertical interconnect portions are included in a first vertical interconnect through the first and second conductive planes that contacts a first contact pad of the first plurality of contact pads.

Abstract: Disclosed herein are integrated circuit (IC) structures with a conductive element coupled to a first surface of a package substrate, where the conductive element has cavities for embedding components and the embedded components are electrically connected to the conductive element, as well as related apparatuses and methods. In some embodiments, embedded components have one terminal end, which may be positioned vertically, with the terminal end facing into the cavity, and coupled to the conductive element. In some embodiments, embedded components have two terminal ends, which may be positioned vertically with one terminal end coupled to the conductive element and the other terminal end coupled to the package substrate. In some embodiments, embedded components include passive devices, such as capacitors, resistors, and inductors. In some embodiments, a conductive element is a stiffener.

Abstract: Over-molded IC package assemblies including an in-mold capacitor. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more capacitors are fabricated within the molding compound. The capacitors may include two or more metal plates separated by an intervening dielectric material, all of which are embedded within a trench in the molding compound. Individual ones of the capacitor plates may physically contact a conductive land of the package redistribution layer or package substrate, for example to tie the plates to a ground plane and power plane, or two supply rails, in a decoupling capacitor application.

Abstract: A stiffener on a semiconductor package substrate includes a plurality of parts that are electrically coupled to the semiconductor package substrate on a die side. Both stiffener parts are electrically contacted through a passive device that is soldered between the two stiffener parts and by an electrically conductive adhesive that bonds a given stiffener part to the semiconductor package substrate. The passive device is embedded between two stiffener parts to create a smaller X-Y footprint as well as a lower Z-direction profile.

Abstract: A stiffener includes an integrated cable-header recess that couples a semiconductor package substrate flexible cable. The flexible cable connects to a device on a board without using interconnections that are arrayed through the board. A semiconductive die is coupled to the semiconductor package substrate and flexible cable through the cable-header recess.