Patents by Inventor Bok Eng Cheah

Bok Eng Cheah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MULTI-FACETED INTEGRATED-CIRCUIT DICE AND PACKAGES
    Publication number: 20200395309
    Abstract: A faceted integrated-circuit die includes a concave facet with an increased interconnect breakout area available to an adjacent device such as a rectangular IC die that is nested within the form factor of the concave facet. The concave facet form factor includes a ledge facet and a main-die facet. Multiple nested faceted IC dice are disclosed for increasing interconnect breakout areas and package miniaturization. A faceted silicon interposer has a concave facet that also provides an increased interconnect breakout area and package miniaturization.
    Type: Application
    Filed: March 13, 2020
    Publication date: December 17, 2020
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Jenny Shio Yin Ong, Seok Ling Lim
  • ELECTRONIC DEVICE AND CROSSTALK MITIGATING SUBSTRATE
    Publication number: 20200388578
    Abstract: A substrate may be included in an electronic device. The substrate may include a first layer that may include a dielectric material. The first layer may define a substrate surface. The substrate may include a second layer optionally including the dielectric material. The second layer may be coupled to the first layer. A wiring trace may be located in the substrate. A recess may extend through the substrate surface, the first layer, and may extend through the second layer. A substrate interconnect may be located within the recess. The substrate interconnect may be at least partially located below the substrate surface. The substrate interconnect may be in electrical communication with the wiring trace.
    Type: Application
    Filed: March 26, 2020
    Publication date: December 10, 2020
    Inventors: Min Suet Lim, Tin Poay Chuah, Bok Eng Cheah, Jackson Chung Peng Kong
  • Transmission line design with routing-over-void compensation
    Patent number: 10856407
    Abstract: Apparatus and methods are provided for ameliorating distortion issues associated with a conductor that passes over a void in a reference plane. In an example, the conductor can include a first part routed over a major surface of a first side of the reference plane structure and that approaches a first edge of the reference plane structure with a first trajectory, a second part routed over the major surface of a second side of the reference plane structure and that approaches a second edge of the reference plane structure with a second trajectory in-line with the first trajectory, and a third portion connecting the first portion with the second portion and having a third trajectory departing from the first trajectory and the second trajectory, the third portion configured to span the void.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Khang Choong Yong, Bok Eng Cheah, Jackson Chung Peng Kong, Stephen Harvey Hall, Yun Rou Lim
  • Interposer with flexible portion
    Patent number: 10840177
    Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Min Suet Lim, Tin Poay Chuah
  • MICRO-HINGE FOR AN ELECTRONIC DEVICE
    Publication number: 20200325711
    Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low profile hinge design that includes a micro-hinge. The micro-hinge can couple a first element to a second element and can include a first attachment that couples to the first element, a second attachment that couples to the second element, and a plurality of linkages that couples the first attachment to the second attachment. The low profile hinge can further include a plurality of micro-hinges and a plurality of support rods.
    Type: Application
    Filed: April 27, 2020
    Publication date: October 15, 2020
    Inventors: Bok Eng Cheah, Howe Yin Loo, Min Suet Lim, Jackson Chung Peng Kong, Poh Tat Oh
  • HYBRID TRANSMISSION LINE
    Publication number: 20200321674
    Abstract: One embodiment provides an apparatus. The apparatus includes a first signal trace and a current return path. The current return path includes a plurality of portions. The plurality of portions includes a first portion, a second portion and a third portion. The first portion is included in a first power plane. The second portion is included in a second power plane coplanar with the first power plane and separated from the first power plane by a split. The third portion spans the split and is included in a reference voltage plane. The reference voltage plane is coplanar with the first signal trace. The reference voltage plane is separated from the first power plane and the second power plane by a dielectric material.
    Type: Application
    Filed: June 30, 2016
    Publication date: October 8, 2020
    Applicant: Intel Corporation
    Inventors: Hungying Lo, Bok Eng Cheah
  • Stairstep interposers with integrated shielding for electronics packages
    Patent number: 10748854
    Abstract: Disclosed herein are stairstep interposers with integrated conductive shields, and related assemblies and techniques. In some embodiments, an interposer may include: an insulating material having a stairstep structure with a first step surface, a second step surface, and a bottom surface to face a package substrate, wherein a first thickness of the insulating material between the first step surface and the bottom surface is greater than a second thickness of the insulating material between the second step surface and the bottom surface; a conductive signal pathway extending from the first step surface to the bottom surface; and a conductive shield disposed within the insulating material to shield the conductive signal pathway.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Hungying Louis Lo
  • Semiconductor package having inductive lateral interconnects
    Patent number: 10734333
    Abstract: Semiconductor packages including a lateral interconnect having an arc segment to increase self-inductance of a signal line is described. In an example, the lateral interconnect includes a circular segment extending around an interconnect pad. The circular segment may extend around a vertical axis of a vertical interconnect to introduce an inductive circuitry to compensate for an impedance mismatch of the vertical interconnect.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Khang Choong Yong, Howard Lincoln Heck
  • Folded semiconductor package architectures and methods of assembling same
    Patent number: 10734318
    Abstract: A fold in a semiconductor package substrate includes an embedded device that includes orthogonal electrical coupling through the package substrate by a bond-pad via that is configured to couple to a semiconductive device that is mounted on the semiconductor package substrate. The semiconductive device is coupled to the embedded device with the orthogonal electrical coupling.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Khang Choong Yong, Yun Rou Lim
  • Fiber weave-sandwiched differential pair routing technique
    Patent number: 10716209
    Abstract: To overcome the problem of the fiber weave effect desynchronizing differential signals in a pair of traces of approximately the same length in a printed circuit board, the pair of traces can be routed to traverse largely parallel paths that are above one another in the printed circuit board. The material between the paths can include weaved fiber bundles. The material on opposite sides of the paths, surrounding the pair of traces and the weaved fiber bundles, can include resin-rich material. As a result, the pair of traces are directly adjacent to the same materials, which can allow signals in the traces to propagate at the same speed, and prevent desynchronization of differential signals traversing the paths. The path length difference associated with traversing to different depths can be compensated with a relatively small in-plane diagonal jog of one of the traces.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: July 14, 2020
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Eng Huat Goh, Jackson Chung Peng Kong, Khang Choong Yong, Min Suet Lim
  • MULTI-ORIENTATION DISPLAY DEVICE
    Publication number: 20200192432
    Abstract: A computing device includes a flexible display screen, a housing to house at least one processor device and at least one memory element, and a first wing to support a side portion of the display screen. The front face of the housing includes a center portion of the display screen. The first wing is connected to the housing by a hinge, the first wing configured to swivel about an axis defined by the hinge. The hinge is configured to lock the first wing in at least two wing positions, a first of the wing positions supports the side portion of the display screen in a first orientation, a second of the wing positions supports the side portion of the display screen in a second orientation, and the side portion of the display screen is active in the first orientation and hidden in the second orientation.
    Type: Application
    Filed: December 9, 2019
    Publication date: June 18, 2020
    Applicant: Intel Corporation
    Inventors: Chee Chun Yee, David W. Browning, Bok Eng Cheah, Jackson Chung Peng Kong, Min Suet Lim, Howe Yin Loo, Poh Tat Oh
  • MULTIPLE-SURFACE CONNECTED EMBEDDED INTERCONNECT BRIDGE FOR SEMICONDUCTOR PACKAGE SUBSTRATES
    Publication number: 20200168538
    Abstract: An embedded interconnect bridge includes a backside trace that can be coupled to a power plane within a semiconductor package substrate. The embedded interconnect bridge-backside trace preserves useful package real estate that is near to where multiple dice are to be mounted on the semiconductor package substrate.
    Type: Application
    Filed: October 24, 2019
    Publication date: May 28, 2020
    Inventors: Jenny Shio Yin Ong, Seok Ling Lim, Bok Eng Cheah, Jackson Chung Peng Kong
  • STACKED-DEVICE THROUGH-SILICON VIAS FOR SEMICONDUCTOR PACKAGES
    Publication number: 20200168528
    Abstract: Disclosed embodiments include a multi-chip package that includes an embedded reference plane between two stacked semiconductive devices, with through-silicon vias that penetrate the reference plane, including reference-voltage vias that contact the reference plane, and signal and power-delivery vias that are insulated from the reference plane. A third semiconductive device is seated with active devices and metallization on the second conductive device.
    Type: Application
    Filed: October 24, 2019
    Publication date: May 28, 2020
    Inventors: Bok Eng Cheah, Seok Ling Lim, Jenny Shio Yin Ong, Jackson Chung Peng Kong
  • EMBEDDED REFERENCE LAYERS FOR SEMICONDUCTOR PACKAGE SUBSTRATES
    Publication number: 20200168559
    Abstract: Two conductive reference layers are embedded in a semiconductor package substrate. The embedded reference layers facilitate low electromagnetic noise coupling between adjacent signals for semiconductor device package.
    Type: Application
    Filed: October 25, 2019
    Publication date: May 28, 2020
    Inventors: Bok Eng Cheah, Seok Ling Lim, Jenny Shio Yin Ong, Jackson Chung Peng Kong, Kooi Chi Ooi
  • SYSTEMS IN PACKAGES INCLUDING WIDE-BAND PHASED-ARRAY ANTENNAS AND METHODS OF ASSEMBLING SAME
    Publication number: 20200168592
    Abstract: A system-in-package includes a package substrate that at least partially surrounds an embedded radio-frequency integrated circuit chip and a processor chip mated to a redistribution layer. A wide-band phased-array antenna module is mated to the package substrate with direct interconnects from the radio-frequency integrated circuit chip to antenna patches within the antenna module. Additionally, fan-out antenna pads are also coupled to the radio-frequency integrated circuit chip.
    Type: Application
    Filed: January 28, 2020
    Publication date: May 28, 2020
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Boon Ping Koh, Kooi Chi Ooi
  • HIGH DENSITY FLEXIBLE INTERCONNECT DESIGN FOR MULTI-MODE SIGNALING
    Publication number: 20200170113
    Abstract: A flexible electronic interconnect comprises a first dielectric layer including a first surface and second surface opposite the first surface; a plurality of conductors disposed on the first surface of the first dielectric layer and arranged spaced apart from each other using a conductor spacing; and a first plurality of conductive shields disposed on the second surface of the first dielectric layer and arranged spaced apart from each other using a conductive shield spacing. The first plurality of conductive shields is arranged opposite the plurality of conductors and the conductive shield spacing is arranged opposite the conductor spacing.
    Type: Application
    Filed: October 24, 2019
    Publication date: May 28, 2020
    Inventors: Chaitanya Sreerama, Bok Eng Cheah, Jackson Chung Peng Kong, Yew San Lim, Stephen Harvey Hall, Eric C. Gantner
  • Mutual inductance suppressor for crosstalk immunity enhancement
    Patent number: 10652999
    Abstract: Embodiments are generally directed to a mutual inductance suppressor for crosstalk immunity enhancement. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer, the second layer including a voltage reference plane; and a mutual inductance suppressor in the voltage reference plane, the mutual inductance suppressor including a serpentine portion of the voltage reference plane between the first signal trace and the second signal trace.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Khang Choong Yong, Jackson Chung Peng Kong, Bok Eng Cheah, Stephen H. Hall
  • Ring-in-ring configurable-capacitance stiffeners and methods of assembling same
    Patent number: 10651127
    Abstract: Ring-in-ring stiffeners on a semiconductor package substrate includes a passive device that is seated across the ring stiffeners. The ring-in-ring stiffeners are also electrically coupled to traces in the semiconductor package substrate through electrically conductive adhesive that bonds a given ring stiffener to the semiconductor package substrate. The passive device is embedded between the two ring stiffeners to create a smaller X-Y footprint as well as a lower Z-direction profile.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Kooi Chi Ooi, Paik Wen Ong
  • Extended stiffener for platform miniaturization
    Patent number: 10643983
    Abstract: Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having a stiffener that extends beyond a package substrate outer edge, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a package substrate having a first side, a second side opposite the first side, and an outer edge extending between the first side and the second side; an IC die coupled with the first side of the package substrate, where the IC die includes a power terminal; a stiffener coupled with the first side of the package substrate, where the stiffener surrounds the IC die and includes a conductive routing region coupled with the IC die power terminal, and a passive electronic device coupled with the conductive routing region. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Bok Eng Cheah, Jackson Chung Peng Kong, Min Suet Lim, Khang Choong Yong, Howe Yin Loo
  • FIBER WEAVE-SANDWICHED DIFFERENTIAL PAIR ROUTING TECHNIQUE
    Publication number: 20200137886
    Abstract: To overcome the problem of the fiber weave effect desynchronizing differential signals in a pair of traces of approximately the same length in a printed circuit board, the pair of traces can be routed to traverse largely parallel paths that are above one another in the printed circuit board. The material between the paths can include weaved fiber bundles. The material on opposite sides of the paths, surrounding the pair of traces and the weaved fiber bundles, can include resin-rich material. As a result, the pair of traces are directly adjacent to the same materials, which can allow signals in the traces to propagate at the same speed, and prevent desynchronization of differential signals traversing the paths. The path length difference associated with traversing to different depths can be compensated with a relatively small in-plane diagonal jog of one of the traces.
    Type: Application
    Filed: September 10, 2019
    Publication date: April 30, 2020
    Inventors: Bok Eng Cheah, Eng Huat Goh, Jackson Chung Peng Kong, Khang Choong Yong, Min Suet Lim