Patents by Inventor Bok Eng Cheah

Bok Eng Cheah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems in packages including wide-band phased-array antennas and methods of assembling same
    Patent number: 10978434
    Abstract: A system-in-package includes a package substrate that at least partially surrounds an embedded radio-frequency integrated circuit chip and a processor chip mated to a redistribution layer. A wide-band phased-array antenna module is mated to the package substrate with direct interconnects from the radio-frequency integrated circuit chip to antenna patches within the antenna module. Additionally, fan-out antenna pads are also coupled to the radio-frequency integrated circuit chip.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Boon Ping Koh, Kooi Chi Ooi
  • Multi-conductor interconnect structure for a microelectronic device
    Patent number: 10980108
    Abstract: A multi-conductor interconnect for a microelectronic device incorporates multiple conductors and integrated shielding for the conductors. The multi-conductor interconnect includes first and second groups of conductors interleaved with one another within a dielectric structure. One of the groups of conductors may be coupled to a reference voltage node to provide shielding for the other group of conductors. The multi-conductor interconnect may further include a shield layer extending over some portion, or all, of the conductors of the first and second groups.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Ping Ping Ooi, Bok Eng Cheah, Jackson Chung Peng Kong, Kooi Chi Ooi
  • Semiconductor package having an impedance-boosting channel
    Patent number: 10971440
    Abstract: Semiconductor package assemblies and semiconductor packages incorporating an impedance-boosting channel between a transmitter die and a receiver die are described. In an example, a semiconductor package includes a package substrate incorporating the impedance-boosting channel having a first arc segment connected to the transmitter die and a second arc segment connected to the receiver die. The arc segments extend around respective vertical axes passing through a transmitter die electrical bump and a receiver die electrical bump, respectively. Accordingly, the arc segments introduce an inductive circuitry to increase signal integrity of an electrical signal sent from the transmitter die to the receiver die.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 6, 2021
    Assignee: Intel Coropration
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Khang Choong Yong, Po Yin Yaw, Kok Hou Teh
  • 3D high-inductive ground plane for crosstalk reduction
    Patent number: 10973116
    Abstract: Embodiments are generally directed to 3D high-inductive ground plane for crosstalk reduction. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer; a third layer below the second layer; and a three-dimensional (3D) ground plane, the 3D ground plane including a first plurality of segments on the third layer, a second plurality of segments on the second layer, and a plurality of metal vias to connect the first plurality of segments and the second plurality of segments in the ground plane.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Khang Choong Yong, Ramaswamy Parthasarathy
  • RECESS BY-PASS INTERCONNECTS
    Publication number: 20210098350
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a circuit board comprising a recess a package in the recess, a semiconductor die coupled to the first side of the package, and a bridge extending from the first side of the package to the circuit board wherein the bridge electrically couples the package to the circuit board.
    Type: Application
    Filed: May 29, 2020
    Publication date: April 1, 2021
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Kooi Chi Ooi, Lee Fueng Yap, Chan Kim Lee
  • Electronic packages with stacked sitffeners and methods of assembling same
    Patent number: 10964677
    Abstract: A semiconductor package apparatus includes a passive device that is embedded in a bottom package stiffener, and a top stiffener is stacked above the bottom package stiffener. Electrical connection through the passive device is accomplished through the stiffeners to a semiconductor die that is seated upon an infield region of the semiconductor package substrate.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Jenny Shio Yin Ong, Bok Eng Cheah, Jackson Chung Peng Kong, Seok Ling Lim, Kooi Chi Ooi
  • Overpass dice stacks and methods of using same
    Patent number: 10957649
    Abstract: A system in package device includes an overpass die on a package substrate and the overpass die includes a recess on the back side in order to straddle a landed die also on the package substrate. The recess is bounded by at least two overpass walls. Communication between the dice is done with a through-silicon via and communication between the overpass die and the package substrate is also done with a through-silicon via.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Min Suet Lim, Jackson Chung Peng Kong
  • Ring-in-ring configurable-capacitance stiffeners and methods of assembling same
    Patent number: 10950552
    Abstract: Ring-in-ring stiffeners on a semiconductor package substrate includes a passive device that is seated across the ring stiffeners. The ring-in-ring stiffeners are also electrically coupled to traces in the semiconductor package substrate through electrically conductive adhesive that bonds a given ring stiffener to the semiconductor package substrate. The passive device is embedded between the two ring stiffeners to create a smaller X-Y footprint as well as a lower Z-direction profile.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Kooi Chi Ooi, Paik Wen Ong
  • 3D stacked-in-recess system in package
    Patent number: 10943792
    Abstract: A system in package device includes a landed first die disposed on a package substrate. The landed first die includes a notch that is contoured and that opens the backside surface of the die to a ledge. A stacked die is mounted at the ledge and the two dice are each contacted by a through-silicon via (TSV). The system in package device also includes a landed subsequent die on the package substrate and a contoured notch in the landed subsequent die and the notch in the first die form a composite contoured recess into which the stacked die is seated.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Min Suet Lim, Jackson Chung Peng Kong, Howe Yin Loo
  • Programmable redistribution die
    Patent number: 10943864
    Abstract: A device and method of utilizing a programmable redistribution die to redistribute the outputs of semiconductor dies. Integrated circuit packages using a programmable redistribution die are shown. Methods of creating a programmable redistribution die are shown.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Min Suet Lim, J-Wing Teh, Bok Eng Cheah
  • FRAME-ARRAY INTERCONNECTS FOR INTEGRATED-CIRCUIT PACKAGES
    Publication number: 20210066185
    Abstract: Disclosed embodiments include frame-array interconnects that have a ledge portion to accommodate a passive device. A seated passive device is between at least two frame-array interconnects for semiconductor package-integrated decoupling capacitors.
    Type: Application
    Filed: June 25, 2020
    Publication date: March 4, 2021
    Inventors: Seok Ling Lim, Jenny Shio Yin Ong, Bok Eng Cheah, Jackson Chung Peng Kong
  • THREE DIMENSIONAL FOLDABLE SUBSTRATE WITH VERTICAL SIDE INTERFACE
    Publication number: 20210051801
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a first rigid substrate, a second rigid substrate, a flexible substrate comprising a first portion attached to the first rigid substrate, a second portion attached to the second rigid substrate, a middle portion connecting the first portion to the second portion, wherein the middle portion is bent, and metallic traces therethrough, and a component forming a direct interface with the middle portion of the flexible substrate, the component electrically coupled to the metallic traces. In selected examples, the device further includes a casing.
    Type: Application
    Filed: May 29, 2020
    Publication date: February 18, 2021
    Inventors: Tin Poay Chuah, Bok Eng Cheah, Jackson Chung Peng Kong
  • Stacked dice systems
    Patent number: 10916524
    Abstract: Discussed generally herein are devices that can include multiple stacked dice electrically coupled to dice electrically coupled to a peripheral sidewall of the stacked dice and/or a dice stack electrically coupled to a passive die. In one or more embodiments a device can include a dice stack comprising at least two dice including a first die and a second die, the first die electrically connected to and on a second die, a first side pad on, or at least partially in, a first sidewall of the dice stack, a third die electrically connected to the first die at a first surface of the third die and through the first side pad, and a fourth die electrically connected to the third die at a second surface of the first die, the second side opposite the first side.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: February 9, 2021
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Kooi Chi Ooi, Ping Ping Ooi
  • Integrated circuit packages with conductive element having cavities housing electrically connected embedded components
    Patent number: 10910325
    Abstract: Disclosed herein are integrated circuit (IC) structures with a conductive element coupled to a first surface of a package substrate, where the conductive element has cavities for embedding components and the embedded components are electrically connected to the conductive element, as well as related apparatuses and methods. In some embodiments, embedded components have one terminal end, which may be positioned vertically, with the terminal end facing into the cavity, and coupled to the conductive element. In some embodiments, embedded components have two terminal ends, which may be positioned vertically with one terminal end coupled to the conductive element and the other terminal end coupled to the package substrate. In some embodiments, embedded components include passive devices, such as capacitors, resistors, and inductors. In some embodiments, a conductive element is a stiffener.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Seok Ling Lim, Jenny Shio Yin Ong, Bok Eng Cheah, Jackson Chung Peng Kong
  • INTERPOSER WITH FLEXIBLE PORTION
    Publication number: 20210028094
    Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.
    Type: Application
    Filed: October 13, 2020
    Publication date: January 28, 2021
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Min Suet Lim, Tin Poay Chuah
  • Vertical modular stiffeners for stacked multi-device packages
    Patent number: 10903155
    Abstract: Disclosed embodiments include a stacked multi-chip package that includes two semiconductor package substrates that are spaced apart by a vertical-device stiffener. The vertical-device stiffener provides both connection space for at least one vertical semiconductive device and at least one vertical radio-frequency device, as well as stiffness and form-factor reduction.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Jenny Shio Yin Ong, Seok Ling Lim
  • Micro through-silicon via for transistor density scaling
    Patent number: 10903142
    Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Tat Hin Tan, Wai Ling Lee
  • PACKAGED DIE STACKS WITH STACKED CAPACITORS AND METHODS OF ASSEMBLING SAME
    Publication number: 20210005547
    Abstract: A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture.
    Type: Application
    Filed: March 16, 2020
    Publication date: January 7, 2021
    Inventors: Bok Eng Cheah, Mooi Ling Chang, Ping Ping Ooi, Jackson Chung Peng Kong, Wen Wei Lum
  • Multiple-layer, self-equalizing interconnects in package substrates
    Patent number: 10886209
    Abstract: A self-equalizing interconnect in a connector is installed in a microelectronic device. The self-equalizing interconnect is formed of a plurality of electrically conductive layers under conditions to offset skin-effect losses with respect to frequency change during operation. Each successive layer is configured to with the next highest electrical conductivity and subsequent electrically conductive films gradually decrease in electrical conductivity. In an embodiment, thickness of the conductive film adjacent the reference plain is configured thinnest and subsequent films are added and are seriatim gradually thicker. The highest electrically conductive film is configured closest to a reference plane in the connector, and the lowest electrically conductive film is farthest from the reference plane.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Stephen Harvey Hall, Bok Eng Cheah, Chaitanya Sreerama, Jackson Chung Peng Kong
  • 3D TRENCH REFERENCE PLANES FOR INTEGRATED-CIRCUIT DIE PACKAGES
    Publication number: 20200395318
    Abstract: A voltage-reference plane has gradient regions that provide altered thicknesses that are useful in a power-deliver network for a semiconductor package substrate. Different signal trace types are located over various portions of the gradient regions to facilitate signal integrity.
    Type: Application
    Filed: March 13, 2020
    Publication date: December 17, 2020
    Inventors: Chin Lee Kuan, Jackson Chung Peng Kong, Bok Eng Cheah