Abstract: An electronic device comprises an integrated circuit (IC) die including a first plurality of contact pads; and a plurality of stacked interconnect layers. The plurality of stacked interconnect layer include a first interconnect layer including a first conductive plane, a first vertical interconnect portion, and dielectric material isolating the first vertical interconnect portion from the first conductive plane; and a second interconnect layer including a second conductive plane contacting the first conductive plane, a second vertical interconnect portion contacting the first vertical interconnect portion, and the dielectric material isolating the second vertical interconnect portion from the second conductive plane; wherein the first and second vertical interconnect portions are included in a first vertical interconnect through the first and second conductive planes that contacts a first contact pad of the first plurality of contact pads.

Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low profile hinge design that includes a micro-hinge. The micro-hinge can couple a first element to a second element and can include a first attachment that couples to the first element, a second attachment that couples to the second element, and a plurality of linkages that couples the first attachment to the second attachment. The low profile hinge can further include a plurality of micro-hinges and a plurality of support rods.

Abstract: The technique described herein includes a device to address the electrical performance (e.g. signal integrity) degradation ascribed to electromagnetic interference and/or crosstalk coupling occur at tightly coupled (e.g. about 110 ?m pitch or less) interconnects, including the first level (e.g. the interconnection between a die and a package substrate). In some embodiments, this invention provides a conductive layer with a plurality of cavities to isolate electromagnetic coupling and/or interference between adjacent interconnects for electronic device performance scaling. In some embodiments, at least one interconnect joint is coupled to the conductive layer, and at least one interconnect joint is isolated from the conductive layer by a dielectric lining at least one of the cavities, the conductive layer being associated to a ground reference voltage by the interconnect joint coupled to the conductive layer.

Abstract: A multiple-damascene structure is located below a semiconductor device footprint on a printed wiring board, where the structure includes multiple recesses that containing useful devices coupled to a semiconductive device.

Abstract: A flexible electronic device that includes a flexible substrate having an upper surface and a lower surface and interconnects extending between the upper surface and the lower surface; a flexible display mounted directly to the upper surface of the flexible substrate such that the flexible display is electrically connected to the flexible substrate; a first encapsulant mounted to the upper surface of the flexible substrate such that the flexible display is at least partially embedded within the first encapsulant; an electronic component mounted to a lower surface of the flexible substrate such that the electronic component is electrically connected to the flexible substrate; a second encapsulant mounted to the lower surface of the flexible substrate such that the electronic component is at least partially embedded within the second encapsulant; a flexible casing that surrounds the electronic component and the second encapsulant.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a first device and a second device coupled to a surface of a substrate, and a continuous flexible shield woven over the first device and under the second device to separate the first device from the second device. In selected examples, the continuous flexible shield may be formed from a laminate and one or more of the devices may be coupled through an opening or via in the continuous flexible shield.

Abstract: Disclosed embodiments include a multi-chip package that includes a stacked through-silicon via in a first semiconductive device, and the first semiconductive device is face-to-face coupled to a second semiconductive device by the stacked through-silicon via. The stacked through-silicon via includes a first portion that contacts a second portion, and the first portion emerges from an active semiconductive region of the first semiconductive device adjacent a keep-out region.

Abstract: A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture.

Abstract: A semiconductor device and associated methods are disclosed. In one example, dies are interconnected through a bridge in a substrate. A reference voltage stack extends over at least a portion of the interconnect bridge, and a passive component is coupled to the reference voltage stack. In one example, the passive component helps to reduce interference in the power supply to components in the semiconductor device, such as the dies and the interconnect bridge.

Abstract: A device and method of utilizing a programmable redistribution die to redistribute the outputs of semiconductor dies. Integrated circuit packages using a programmable redistribution die are shown. Methods of creating a programmable redistribution die are shown.

Abstract: Discussed generally herein are devices that can include multiple stacked dice electrically coupled to dice electrically coupled to a peripheral sidewall of the stacked dice and/or a dice stack electrically coupled to a passive die. In one or more embodiments a device can include a dice stack comprising at least two dice including a first die and a second die, the first die electrically connected to and on a second die, a first side pad on, or at least partially in, a first sidewall of the dice stack, a third die electrically connected to the first die at a first surface of the third die and through the first side pad, and a fourth die electrically connected to the third die at a second surface of the first die, the second side opposite the first side.

Abstract: A multi-conductor interconnect for a microelectronic device incorporates multiple conductors and integrated shielding for the conductors. The multi-conductor interconnect includes first and second groups of conductors interleaved with one another within a dielectric structure. One of the groups of conductors may be coupled to a reference voltage node to provide shielding for the other group of conductors. The multi-conductor interconnect may further include a shield layer extending over some portion, or all, of the conductors of the first and second groups.

Abstract: A system-in-package includes a package substrate that at least partially surrounds an embedded radio-frequency integrated circuit chip and a processor chip mated to a redistribution layer. A wide-band phased-array antenna module is mated to the package substrate with direct interconnects from the radio-frequency integrated circuit chip to antenna patches within the antenna module. Additionally, fan-out antenna pads are also coupled to the radio-frequency integrated circuit chip.

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a base package, an ancillary package, and an electrically isolated metal layer. The base package may include a base die. The ancillary package may include an ancillary component. The ancillary package may be located on top of the base package. The electrically isolated metal layer may be located at least partially within a layer of the base package such that a portion of the electrically isolated metal layer contacts at least one surface of the base die and is located in between the base die and the ancillary component.

Abstract: Over-molded IC package assemblies including an embedded voltage reference plane and/or heat spreader. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more conductive layers are embedded within the molding compound. The conductive layers may include an interior portion located over the IC chip and a peripheral portion located over the redistribution layers or package substrate. The interior portion may comprise one or more heat conductive features, which may physically contact a surface of the IC chip. In some further embodiments, the peripheral portion comprises one or more electrically conductive features, which may physically contact a surface of the package redistribution layers or package substrate to convey a reference voltage.

Abstract: To maintain the integrity of electrical contacts at a build-up layer of a chip package, while reducing electrical interference caused by a chip connected to the build-up layer, the chip package can include a stiffener formed from an electrically conductive material and positioned between the chip and the build-up layer. The chip can electrically connect to the build-up layer through electrical connections that extend through the stiffener. Compared with a stiffener that extends only over a single chip of the chip package, the present stiffener can help prevent warpage or other mechanical deformities that can degrade electrical contacts away from the chip at the build-up layer. Compared with a stiffener that extends only over an area away from the chip, such as a peripheral area, the present stiffener can help reduce electrical interference in an area of the build-up layer near the chip.

Abstract: A stiffener includes an integrated cable-header recess that couples a semiconductor package substrate flexible cable. The flexible cable connects to a device on a board without using interconnections that are arrayed through the board. A semiconductive die is coupled to the semiconductor package substrate and flexible cable through the cable-header recess.

Abstract: To overcome the problem of devices in a multi-chip package (MCP) interfering with one another, such as through electromagnetic interference (EMI) and/or radio-frequency interference (RFI), the chip package can include an electrically conductive stiffener that at least partially electrically shields the devices from one another. At least some of the devices can be positioned in respective recesses in the stiffener. In some examples, when the devices are positioned in the recesses, at least one device does not extend beyond a plane defined by a first side of the stiffener. Such shielding can help reduce interference between the devices. Because device-to-device electrical interference can be reduced, devices on the package can be positioned closer to one another, thereby reducing a size of the package. The devices can electrically connect to a substrate via electrical connections that extend through the stiffener.

Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.