Patents by Inventor Bor-Zen Tien
Bor-Zen Tien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9299621Abstract: An integrated circuit includes a number of lateral diffusion measurement structures arranged on a silicon substrate. A lateral diffusion measurement structure includes a p-type region and an n-type region which cooperatively span a predetermined initial distance between opposing outer edges of the lateral diffusion measurement structure. The p-type and n-type regions meet at a p-n junction expected to be positioned at a target junction location after dopant diffusion has occurred.Type: GrantFiled: September 12, 2013Date of Patent: March 29, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Wei Yang, Yi-Ruei Lin, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
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Patent number: 9299658Abstract: A semiconductor device with the metal fuse and a fabricating method thereof are provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.Type: GrantFiled: May 20, 2015Date of Patent: March 29, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Chung Lai, Kang-Min Kuo, Yen-Ming Peng, Gwo-Chyuan Kuoh, Han-Wei Yang, Yi-Ruei Lin, Chin-Chia Chang, Ying-Chieh Liao, Che-Chia Hsu, Bor-Zen Tien
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Publication number: 20160064567Abstract: Embodiments of the present disclosure relate generally to a semiconductor device and method of fabricating the same, the semiconductor device includes a semiconductor substrate and a gate stack disposed over a channel region of the semiconductor device, the gate stack includes an oxidation layer, a gate dielectric and a gate electrode, the oxidation layer at least covers a portion of the channel region of the semiconductor device and may act as a barrier to prevent damage to the underlying features, such as the source and drain regions, during removal of a dummy gate in a gate last process.Type: ApplicationFiled: September 2, 2014Publication date: March 3, 2016Inventors: Wei-Shuo HO, Chia-Ming CHANG, Tsung-Yu CHIANG, Kuang-Hsin CHEN, Bor-Zen TIEN
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Publication number: 20160043038Abstract: Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.Type: ApplicationFiled: October 23, 2015Publication date: February 11, 2016Inventors: Tsung-Yu Chiang, Chen Kuang-Hsin, Bor-Zen Tien, Tzong-Sheng Chang
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Publication number: 20160042992Abstract: A method comprises forming a plurality of interconnect components over a gate structure, wherein a bottom metal line of the interconnect components is connected to the gate structure through a gate plug, depositing a dielectric layer over a top metal line of the interconnect components, forming an opening in the dielectric layer, depositing a first barrier layer on a bottom and sidewalls of the opening using a non-plasma based deposition process, depositing a second barrier layer over the first barrier layer using a plasma based deposition process and forming a pad in the opening.Type: ApplicationFiled: October 20, 2015Publication date: February 11, 2016Inventors: Bor-Zen Tien, Jhu-Ming Song, Hsuan-Han Lin, Kuang-Hsin Chen, Mu-Yi Lin, Tzong-Sheng Chang
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Publication number: 20160043003Abstract: Methods for forming a semiconductor device are provided. The method includes forming a first fin and a second fin over a substrate and forming a first isolation structures and a second isolation structure adjacent to the substrate. The first fin is partially surrounded by the first isolation structure and a second fin is partially surrounded by the second isolation structure, and the first isolation structure has a dopant concentration higher than that of the second isolation structure.Type: ApplicationFiled: October 21, 2015Publication date: February 11, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Yu CHIANG, Chung-Wei LIN, Kuang-Hsin CHEN, Bor-Zen TIEN
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Patent number: 9252259Abstract: Methods and devices for forming a contact over a metal gate for a transistor are provided. The device may comprise an active area, an isolation area surrounding the active area, and a metal gate above the isolation area, wherein the metal gate comprises a conductive layer. The contact comprises a first contact part within the conductive layer, above the isolation area without vertically overlapping the active area, and a second contact part above the first contact part, connected to the first contact part, and substantially vertically contained within the first contact part.Type: GrantFiled: February 21, 2013Date of Patent: February 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen, Bor-Zen Tien, Tzong-Sheng Chang
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Patent number: 9190319Abstract: A method for forming interconnect structures comprises forming a metal line made of a first conductive material over a substrate, depositing a dielectric layer over the metal line, patterning the dielectric layer to form an opening, depositing a first barrier layer on a bottom and sidewalls of the opening using an atomic layer deposition technique, depositing a second barrier layer over the first barrier layer, wherein the first barrier layer is coupled to ground and forming a pad made of a second conductive material in the opening.Type: GrantFiled: March 8, 2013Date of Patent: November 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsuan-Han Lin, Jhu-Ming Song, Mu-Yi Lin, Kuang-Hsin Chen, Bor-Zen Tien, Tzong-Sheng Chang
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Patent number: 9184087Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a first fin partially surrounded by a first isolation structure and protruding through a top surface thereof. The semiconductor device also includes a second fin partially surrounded by a second isolation structure and protruding through a top surface thereof. The top surface of the first isolation structure is higher than the top surface of the second isolation structure such that the second fin has a height higher than that of the first fin. The second isolation structure has a dopant concentration higher than that of the first isolation structure.Type: GrantFiled: December 27, 2013Date of Patent: November 10, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Yu Chiang, Chung-Wei Lin, Kuang-Hsin Chen, Bor-Zen Tien
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Patent number: 9178066Abstract: Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.Type: GrantFiled: August 30, 2013Date of Patent: November 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Tsung-Yu Chiang, Chen Kuang-Hsin, Bor-Zen Tien, Tzong-Sheng Chang
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Publication number: 20150311156Abstract: A semiconductor device having enhanced passivation integrity is disclosed. The device includes a substrate, a first layer, and a metal layer. The first layer is formed over the substrate. The first layer includes a via opening and a tapered portion proximate to the via opening. The metal layer is formed over the via opening and the tapered portion of the first layer. The metal layer is substantially free from gaps and voids.Type: ApplicationFiled: July 6, 2015Publication date: October 29, 2015Inventors: Ying-Chieh Liao, Han-Wei Yang, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
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Publication number: 20150255394Abstract: A semiconductor device with the metal fuse and a fabricating method thereof are provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.Type: ApplicationFiled: May 20, 2015Publication date: September 10, 2015Inventors: Chen-Chung LAI, Kang-Min KUO, Yen-Ming PENG, Gwo-Chyuan KUOH, Han-Wei YANG, Yi-Ruei LIN, Chin-Chia CHANG, Ying-Chieh LIAO, Che-Chia HSU, Bor-Zen TIEN
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Patent number: 9122828Abstract: A system and method of designing a layout for a plurality of different logic operation (LOP) cell technologies includes defining a priority for each LOP cell technology in the plurality of different LOP technologies and forming a layout of the plurality of different LOP cells for formation on a substrate with at least some of the LOP cells of higher priority LOP technologies overlapping LOP cells of lower priority LOP technologies. The system can include a processor coupled to memory where stored code defines the priority for each different cell technology in the plurality of LOP cells and (when the code is executed) the processor forms the layout of a plurality of different LOP cells. All of the LOP cells of higher priority LOP technologies overlap LOP cells of lower priority. The system or method also avoids the overlap of higher priority LOP cells by lower priority LOP cells.Type: GrantFiled: May 17, 2013Date of Patent: September 1, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen, Song-Bor Lee, Bor-Zen Tien, Tzong-Sheng Chang
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Patent number: 9093528Abstract: The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) stress compensation layers that reduce stress on one or more underlying semiconductor devices, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices. A stressed element is located within a back-end-of-the-line stack at a position overlying the one or more semiconductor devices. A stressing layer is located over the stressed element induces a stress upon the stressed element. A stress compensation layer, located over the stressed element, provides a counter-stress to reduce the stress induced on the stressed element by the stressing layer. By reducing the stress induced on the stressed element, stress on the semiconductor substrate is reduced, improving uniformity of performance of the one or more semiconductor devices.Type: GrantFiled: May 30, 2013Date of Patent: July 28, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Ming Peng, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
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Patent number: 9093373Abstract: An integrated circuit includes a p-type region formed beneath a surface of a semiconductor substrate, and an n-type region formed beneath the surface of the semiconductor substrate. The n-type region meets the p-type region at a p-n junction. A diffusion barrier structure, which is beneath the surface of the semiconductor substrate and extends along a side of the p-n junction, limits lateral diffusion between the p-type region and n-type region.Type: GrantFiled: August 13, 2013Date of Patent: July 28, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Chia Chang, Han-Wei Yang, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
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Patent number: 9076804Abstract: A semiconductor device having enhanced passivation integrity is disclosed. The device includes a substrate, a first layer, and a metal layer. The first layer is formed over the substrate. The first layer includes a via opening and a tapered portion proximate to the via opening. The metal layer is formed over the via opening and the tapered portion of the first layer. The metal layer is substantially free from gaps and voids.Type: GrantFiled: August 23, 2013Date of Patent: July 7, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ying-Chieh Liao, Han-Wei Yang, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
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Publication number: 20150187634Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a first fin partially surrounded by a first isolation structure and protruding through a top surface thereof. The semiconductor device also includes a second fin partially surrounded by a second isolation structure and protruding through a top surface thereof. The top surface of the first isolation structure is higher than the top surface of the second isolation structure such that the second fin has a height higher than that of the first fin. The second isolation structure has a dopant concentration higher than that of the first isolation structure.Type: ApplicationFiled: December 27, 2013Publication date: July 2, 2015Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Tsung-Yu CHIANG, Chung-Wei LIN, Kuang-Hsin CHEN, Bor-Zen TIEN
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Patent number: 9070687Abstract: A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.Type: GrantFiled: June 28, 2013Date of Patent: June 30, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Chung Lai, Kang-Min Kuo, Yen-Ming Peng, Gwo-Chyuan Kuoh, Han-Wei Yang, Yi-Ruei Lin, Chin-Chia Chang, Ying-Chieh Liao, Che-Chia Hsu, Bor-Zen Tien
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Publication number: 20150069395Abstract: An integrated circuit includes a number of lateral diffusion measurement structures arranged on a silicon substrate. A lateral diffusion measurement structure includes a p-type region and an n-type region which cooperatively span a predetermined initial distance between opposing outer edges of the lateral diffusion measurement structure. The p-type and n-type regions meet at a p-n junction expected to be positioned at a target junction location after dopant diffusion has occurred.Type: ApplicationFiled: September 12, 2013Publication date: March 12, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Wei Yang, Yi-Ruei Lin, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
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Publication number: 20150061016Abstract: Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Inventors: Tsung-Yu Chiang, Chen Kuang-Hsin, Bor-Zen Tien, Tzong-Sheng Chang