Patents by Inventor Bor-Zen Tien
Bor-Zen Tien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150054163Abstract: A semiconductor device having enhanced passivation integrity is disclosed. The device includes a substrate, a first layer, and a metal layer. The first layer is formed over the substrate. The first layer includes a via opening and a tapered portion proximate to the via opening. The metal layer is formed over the via opening and the tapered portion of the first layer. The metal layer is substantially free from gaps and voids.Type: ApplicationFiled: August 23, 2013Publication date: February 26, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ying-Chieh Liao, Han-Wei Yang, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
-
Publication number: 20150048507Abstract: An integrated circuit includes a p-type region formed beneath a surface of a semiconductor substrate, and an n-type region formed beneath the surface of the semiconductor substrate. The n-type region meets the p-type region at a p-n junction. A diffusion barrier structure, which is beneath the surface of the semiconductor substrate and extends along a side of the p-n junction, limits lateral diffusion between the p-type region and n-type region.Type: ApplicationFiled: August 13, 2013Publication date: February 19, 2015Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Chin-Chia Chang, Han-Wei Yang, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
-
Publication number: 20150001592Abstract: A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Applicant: Taiwan Semiconductor Manufacturing Co., LTD.Inventors: Chen-Chung Lai, Kang-Min Kuo, Yen-Ming Peng, Gwo-Chyuan Kuoh, Han-Wei Yang, Yi-Ruei Lin, Chin-Chia Chang, Ying-Chieh Liao, Che-Chia Hsu, Bor-Zen Tien
-
Publication number: 20140374832Abstract: The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) selectivity stress films that apply a stress that improves the performance of semiconductor devices underlying the BEOL selectivity stress films, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices having a first device type. A stress transfer element is located within a back-end-of-the-line stack at a position over the one or more semiconductor devices. A selectivity stress film is located over the stress transfer element. The selectivity stress film induces a stress upon the stress transfer element, wherein the stress has a compressive or tensile state depending on the first device type of the one or more semiconductor devices. The stress acts upon the one or more semiconductor devices to improve their performance.Type: ApplicationFiled: June 24, 2013Publication date: December 25, 2014Inventors: Gwo-Chyuan Kuoh, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien, Yen-Ming Peng
-
Publication number: 20140353833Abstract: The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) stress compensation layers that reduce stress on one or more underlying semiconductor devices, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices. A stressed element is located within a back-end-of-the-line stack at a position overlying the one or more semiconductor devices. A stressing layer is located over the stressed element induces a stress upon the stressed element. A stress compensation layer, located over the stressed element, provides a counter-stress to reduce the stress induced on the stressed element by the stressing layer. By reducing the stress induced on the stressed element, stress on the semiconductor substrate is reduced, improving uniformity of performance of the one or more semiconductor devices.Type: ApplicationFiled: May 30, 2013Publication date: December 4, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Ming Peng, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
-
Publication number: 20140344770Abstract: A system and method of designing a layout for a plurality of different logic operation (LOP) cell technologies includes defining a priority for each LOP cell technology in the plurality of different LOP technologies and forming a layout of the plurality of different LOP cells for formation on a substrate with at least some of the LOP cells of higher priority LOP technologies overlapping LOP cells of lower priority LOP technologies. The system can include a processor coupled to memory where stored code defines the priority for each different cell technology in the plurality of LOP cells and (when the code is executed) the processor forms the layout of a plurality of different LOP cells. All of the LOP cells of higher priority LOP technologies overlap LOP cells of lower priority. The system or method also avoids the overlap of higher priority LOP cells by lower priority LOP cells.Type: ApplicationFiled: May 17, 2013Publication date: November 20, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Yu CHIANG, Kuang-Hsin Chen, Song-Bor Lee, Bor-Zen Tien, Tzong-Sheng Chang
-
Patent number: 8860151Abstract: A semiconductor device includes a gate structure over a substrate. The device further includes an isolation feature in the substrate and adjacent to an edge of the gate structure. The device also includes a spacer overlying a sidewall of the gate structure. The spacer has a bottom lower than a top surface of the substrate.Type: GrantFiled: March 1, 2013Date of Patent: October 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Ching Chen, Kuang-Hsin Chen, Bor-Zen Tien, Tzong-Sheng Chang
-
Publication number: 20140252621Abstract: A method for forming interconnect structures comprises forming a metal line made of a first conductive material over a substrate, depositing a dielectric layer over the metal line, patterning the dielectric layer to form an opening, depositing a first barrier layer on a bottom and sidewalls of the opening using an atomic layer deposition technique, depositing a second barrier layer over the first barrier layer, wherein the first barrier layer is coupled to ground and forming a pad made of a second conductive material in the opening.Type: ApplicationFiled: March 8, 2013Publication date: September 11, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsuan-Han Lin, Jhu-Ming Song, Mu-Yi Lin, Kuang-Hsin Chen, Bor-Zen Tien, Tzong-Sheng Chang
-
Publication number: 20140246709Abstract: A semiconductor device includes a gate structure over a substrate. The device further includes an isolation feature in the substrate and adjacent to an edge of the gate structure. The device also includes a spacer overlying a sidewall of the gate structure. The spacer has a bottom lower than a top surface of the substrate.Type: ApplicationFiled: March 1, 2013Publication date: September 4, 2014Inventors: Sheng-Ching Chen, Kuang-Hsin Chen, Bor-Zen Tien, Tzong-Sheng Chang
-
Publication number: 20140231932Abstract: Methods and devices for forming a contact over a metal gate for a transistor are provided. The device may comprise an active area, an isolation area surrounding the active area, and a metal gate above the isolation area, wherein the metal gate comprises a conductive layer. The contact comprises a first contact part within the conductive layer, above the isolation area without vertically overlapping the active area, and a second contact part above the first contact part, connected to the first contact part, and substantially vertically contained within the first contact part.Type: ApplicationFiled: February 21, 2013Publication date: August 21, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen, Bor-Zen Tien, Tzong-Sheng Chang
-
Patent number: 7998772Abstract: A method for forming a protection diode utilizes processing operations and materials used in the formation of the CMOS integrated circuit device and provides a protection diode used in CMOS integrated circuit devices to direct charged particles to benign locations and prevent damage to the devices. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations.Type: GrantFiled: December 3, 2009Date of Patent: August 16, 2011Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Bor-Zen Tien, Tzong-Sheng Chang, Yung-Fu Shen, Jieh-Ting Chang
-
Publication number: 20100081249Abstract: A method for forming a protection diode utilizes processing operations and materials used in the formation of the CMOS integrated circuit device and provides a protection diode used in CMOS integrated circuit devices to direct charged particles to benign locations and prevent damage to the devices. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations.Type: ApplicationFiled: December 3, 2009Publication date: April 1, 2010Inventors: Bor-Zen Tien, Tzong-Sheng Chang, Yung-Fu Shen, Jieh-Ting Chang
-
Patent number: 7663164Abstract: A protection diode is used in a CMOS integrated circuit device to direct charged particles to benign locations and prevent damage to the device. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations. The method for forming the structure utilizes processing operations and materials used in the formation of the CMOS integrated circuit device.Type: GrantFiled: January 26, 2005Date of Patent: February 16, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bor-Zen Tien, Tzong-Sheng Chang, Yung-Fu Shen, Jieh-Ting Chang
-
Publication number: 20060163657Abstract: A protection diode is used in a CMOS integrated circuit device to direct charged particles to benign locations and prevent damage to the device. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations. The method for forming the structure utilizes processing operations and materials used in the formation of the CMOS integrated circuit device.Type: ApplicationFiled: January 26, 2005Publication date: July 27, 2006Inventors: Bor-Zen Tien, Tzong-Sheng Chang, Yung-Fu Shen, Jieh-Ting Chang
-
Patent number: 6346449Abstract: A method for fabricating a junction for a field effect transistor which does not cause distortion of the sidewall spacers during subsequent processing thereby reducing junction depletion and source to drain leakage. The process begins by providing a substrate structure having a gate thereon. Sidewall spacers are formed on the sidewalls of the gate. Impurity ions are implanted into the substrate structure adjacent to the gate to form source and drain regions. A resist protect oxide layer is formed over the substrate structure. The resist protect oxide is patterned by forming a mask over the resist protect oxide layer having an opening over the gate and the source and drain regions. The resist protect oxide layer is selectively etched; thereby removing the resist protect oxide over the source and drain regions without distorting the sidewall spacers. A silicide region is formed on the source and drain regions using a salicide process comprising a pre-amorphous implant and one or more rapid thermal anneal steps.Type: GrantFiled: May 17, 1999Date of Patent: February 12, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Tzong-Sheng Chang, Shih-Chang Huang, Bor-Zen Tien, Chen Cheng Chou
-
Patent number: 6294448Abstract: A new method is provided for the formation of silicided layers over points of electrical contact that are required in MOSFET devices. The structure of the MOSFET gate electrode is formed, including LDD regions, gate spacers and source/drain regions. A layer of Resist Protective Oxide (RPO) is deposited over the structure and patterned leaving the RPO in place where the silicided layers are not to be formed and exposing surfaces on which salicided layers are to be formed. These surfaces are the surfaces of the substrate overlying the source and drain regions and the surface of the gate electrode. An extra As or BF2 implant is performed into the surface of the exposed regions after which the process of salicidation is performed following conventional processing steps.Type: GrantFiled: January 18, 2000Date of Patent: September 25, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Tzong-Sheng Chang, Hung-Chi Tsai, Bor-Zen Tien
-
Patent number: 6284611Abstract: This invention provides a method for forming a self-aligned silicide with low sheet resistance in the N+ source and drain regions and the N+ polysilicon regions in a semiconductor device using a titanium nitride barrier layer to prevent nitridation of an underlying titanium layer during rapid thermal anneal. The process begins by providing a substrate structure having a gate thereon. A titanium layer is deposited over the substrate structure and the gate. Mixing ions are implanted through the titanium layer into source and drain regions adjacent to the gate. A titanium nitride barrier layer is deposited on the titanium layer. The substrate structure is rapid thermal annealed causing the titanium layer to react with the underlying silicon to form silicide. The substrate structure is selectively etched to remove the titanium nitride barrier layer and unreacted titanium. A second rapid thermal anneal is performed.Type: GrantFiled: December 20, 1999Date of Patent: September 4, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Bor-Zen Tien, Tzong-Sheng Chang, Chen-Cheng Chou, Wen-Jye Yue