Patents by Inventor Brad Eaton

Brad Eaton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190291206
    Abstract: Methods of dicing semiconductor wafers are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a material layer over and between the plurality of singulated dies above the dicing tape. The method also includes expanding the dicing tape, wherein a plurality of particles is collected on the material layer during the expanding.
    Type: Application
    Filed: June 12, 2019
    Publication date: September 26, 2019
    Inventors: Wei-Sheng Lei, Jungrae Park, Ajay Kumar, Brad Eaton
  • Patent number: 10363629
    Abstract: Methods of dicing semiconductor wafers are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a material layer over and between the plurality of singulated dies above the dicing tape. The method also includes expanding the dicing tape, wherein a plurality of particles is collected on the material layer during the expanding.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 30, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Jungrae Park, Ajay Kumar, Brad Eaton
  • Publication number: 20190088549
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.
    Type: Application
    Filed: November 16, 2018
    Publication date: March 21, 2019
    Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
  • Patent number: 10163713
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: December 25, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
  • Publication number: 20180345418
    Abstract: Methods of dicing semiconductor wafers are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a material layer over and between the plurality of singulated dies above the dicing tape. The method also includes expanding the dicing tape, wherein a plurality of particles is collected on the material layer during the expanding.
    Type: Application
    Filed: June 1, 2017
    Publication date: December 6, 2018
    Inventors: Wei-Sheng Lei, Jungrae Park, Ajay Kumar, Brad Eaton
  • Publication number: 20180342422
    Abstract: Light-absorbing masks and methods of dicing semiconductor wafers are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits involves forming a mask above the semiconductor wafer. The mask includes a water-soluble matrix based on a solid component and water, and a light-absorber species throughout the water-soluble matrix. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask with gaps and corresponding trenches in the semiconductor wafer in regions between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the patterned mask to extend the trenches and to singulate the integrated circuits. The patterned mask protects the integrated circuits during the plasma etching.
    Type: Application
    Filed: May 26, 2017
    Publication date: November 29, 2018
    Inventors: Wenguang Li, James S. Papanu, Wei-Sheng Lei, Prabhat Kumar, Brad Eaton, Ajay Kumar, Alexander N. Lerner
  • Publication number: 20180226355
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a split laser beam laser scribing process, such as a split shaped laser beam laser scribing process, to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Application
    Filed: April 5, 2018
    Publication date: August 9, 2018
    Inventors: JUNGRAE PARK, WEI-SHENG LEI, BRAD EATON, JAMES S. PAPANU, AJAY KUMAR
  • Patent number: 9972575
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a split laser beam laser scribing process, such as a split shaped laser beam laser scribing process, to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: May 15, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Jungrae Park, Wei-Sheng Lei, Brad Eaton, James S. Papanu, Ajay Kumar
  • Patent number: 9852997
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a rotating laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: December 26, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Jungrae Park, Wei-Sheng Lei, James S. Papanu, Brad Eaton, Ajay Kumar
  • Patent number: 9793132
    Abstract: Etch masks and methods of dicing semiconductor wafers are described. In an example, an etch mask for a wafer singulation process includes a water-soluble matrix based on a solid component and water. The etch mask also includes a plurality of particles dispersed throughout the water-soluble matrix. The plurality of particles has an average diameter approximately in the range of 5-100 nanometers. A ratio of weight % of the solid component to weight % of the plurality of particles is approximately in the range of 1:0.1-1:4.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: October 17, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Wenguang Li, James S. Papanu, Ramesh Krishnamurthy, Prabhat Kumar, Brad Eaton, Ajay Kumar, Alexander N. Lerner
  • Publication number: 20170278801
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a rotating laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Application
    Filed: March 25, 2016
    Publication date: September 28, 2017
    Inventors: Jungrae Park, Wei-Sheng Lei, James S. Papanu, Brad Eaton, Ajay Kumar
  • Patent number: 9768014
    Abstract: Improved wafer coating processes, apparatuses, and systems are described. In one embodiment, an improved spin-coating process and system is used to form a mask for dicing a semiconductor wafer with a laser plasma dicing process. In one embodiment, a spin-coating apparatus for forming a film over a semiconductor wafer includes a rotatable stage configured to support the semiconductor wafer. The rotatable stage has a downward sloping region positioned beyond a perimeter of the semiconductor wafer. The apparatus includes a nozzle positioned above the rotatable stage and configured to dispense a liquid over the semiconductor wafer. The apparatus also includes a motor configured to rotate the rotatable stage.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: September 19, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Jungrae Park, Wei-Sheng Lei, Prabhat Kumar, James S. Papanu, Brad Eaton, Ajay Kumar
  • Publication number: 20170256500
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a split laser beam laser scribing process, such as a split shaped laser beam laser scribing process, to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Application
    Filed: March 3, 2016
    Publication date: September 7, 2017
    Inventors: Jungrae Park, Wei-Sheng Lei, Brad Eaton, James S. Papanu, Ajay Kumar
  • Patent number: 9721839
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits includes forming a water soluble mask above the semiconductor wafer, the water soluble mask covering and protecting the integrated circuits. The method also includes baking the water soluble mask to increase the etch resistance of the water soluble mask. The method also includes, subsequent to baking the water soluble mask, patterning the water soluble mask with a laser scribing process to provide a water soluble patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also includes plasma etching the semiconductor wafer through the gaps in the water soluble patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: August 1, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Mohammad Kamruzzaman Chowdhury, Brad Eaton, Ajay Kumar
  • Patent number: 9620379
    Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a multi-layered mask comprising a laser energy absorbing, non-photodefinable topcoat disposed over a water-soluble base layer disposed over the semiconductor substrate. Because the laser light absorbing material layer is non-photodefinable, material costs associated with conventional photo resist formulations may be avoided. The mask is direct-write patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. Absorption of the mask layer within the laser emission band (e.g., UV band and/or green band) promotes good scribe line quality. The substrate may then be plasma etched through the gaps in the patterned mask to singulate the IC with the mask protecting the ICs during the plasma etch. The soluble base layer of the mask may then be dissolved subsequent to singulation, facilitating removal of the layer.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: April 11, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Mohammad Kamruzzaman Chowdhury, Todd Egan, Brad Eaton, Madhava Rao Yalamanchili, Ajay Kumar
  • Patent number: 9601375
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side of the semiconductor wafer includes adhering a back side the semiconductor wafer on the dicing tape of a substrate carrier. Subsequent to adhering the semiconductor wafer on a dicing tape, the dicing tape is treated with a UV-cure process. Subsequent to treating the dicing tape with the UV-cure process, a dicing mask is formed on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits. The dicing mask is patterned with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the dicing mask layer to singulate the integrated circuits.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: March 21, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Jungrae Park, Ajay Kumar, James S. Papanu, Prabhat Kumar
  • Patent number: 9583375
    Abstract: Methods and systems for forming water soluble masks by dry film lamination are described. Also described are methods of wafer dicing, including formation of a water soluble mask by dry film lamination. In one embodiment, a method involves moisturizing an inner area of a water soluble dry film. The method involves stretching the water soluble dry film over a surface of the semiconductor wafer, and attaching the moistened inner area of the stretched film to the surface of the semiconductor wafer. A method of wafer dicing may further involve patterning the water soluble dry film, exposing regions of the semiconductor wafer between the ICs, and etching the semiconductor wafer through gaps in the patterned water soluble dry film.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: February 28, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, James S. Papanu, Brad Eaton, Ajay Kumar
  • Publication number: 20160365283
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits includes forming a water soluble mask above the semiconductor wafer, the water soluble mask covering and protecting the integrated circuits. The method also includes baking the water soluble mask to increase the etch resistance of the water soluble mask. The method also includes, subsequent to baking the water soluble mask, patterning the water soluble mask with a laser scribing process to provide a water soluble patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also includes plasma etching the semiconductor wafer through the gaps in the water soluble patterned mask to singulate the integrated circuits.
    Type: Application
    Filed: June 12, 2015
    Publication date: December 15, 2016
    Inventors: Wei-Sheng Lei, Mohammad Kamruzzaman Chowdhury, Brad Eaton, Ajay Kumar
  • Publication number: 20160315009
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side of the semiconductor wafer includes adhering a back side the semiconductor wafer on the dicing tape of a substrate carrier. Subsequent to adhering the semiconductor wafer on a dicing tape, the dicing tape is treated with a UV-cure process. Subsequent to treating the dicing tape with the UV-cure process, a dicing mask is formed on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits. The dicing mask is patterned with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the dicing mask layer to singulate the integrated circuits.
    Type: Application
    Filed: April 27, 2015
    Publication date: October 27, 2016
    Inventors: Wei-Sheng Lei, Brad Eaton, Jungrae Park, Ajay Kumar, James S. Papanu, Prabhat Kumar
  • Patent number: 9460966
    Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a front surface having a plurality of integrated circuits thereon involves forming a mask layer above the front surface of the semiconductor wafer. The method also involves laser scribing the mask layer and the front surface of the semiconductor wafer to provide scribe lines in the mask layer and partially into the semiconductor wafer. The laser scribing involves use of a dual focus lens to provide a dual focus spot beam. The method also involves etching the semiconductor wafer through the scribe lines to singulate the integrated circuits.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: October 4, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Ajay Kumar