Patents by Inventor Brad Eaton

Brad Eaton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9224625
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The semiconductor wafer is disposed on a water-soluble die attach film. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The water-soluble die attach film is then patterned with an aqueous solution.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: December 29, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Madhava Rao Yalamanchili, Brad Eaton, Saravjeet Singh, Ajay Kumar
  • Patent number: 9224650
    Abstract: Approaches for backside laser scribe plus front side laser scribe and plasma etch dicing of a wafer or substrate are described. For example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side thereof and metallization on a backside thereof involves patterning the metallization on the backside with a first laser scribing process to provide a first plurality of laser scribe lines on the backside. The method also involves forming a mask on the front side. The method also involves patterning, from the front side, the mask with a second laser scribing process to provide a patterned mask with a second plurality of scribe lines exposing regions of the semiconductor wafer between the integrated circuits, wherein the second plurality of scribe lines is aligned with the first plurality of scribe lines. The method also involves plasma etching the semiconductor wafer through the second plurality of scribe lines to singulate the integrated circuits.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: December 29, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Ajay Kumar
  • Patent number: 9218992
    Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The semiconductor wafer is supported by a substrate carrier. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits while supported by the substrate carrier.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: December 22, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Saravjeet Singh, Brad Eaton, Ajay Kumar, Wei-Sheng Lei, James M. Holden, Madhava Rao Yalamanchili, Todd J. Egan
  • Patent number: 9209084
    Abstract: Maskless hybrid laser scribing and plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer having a front surface with a plurality of integrated circuits thereon and having a passivation layer disposed between and covering metal pillar/solder bump pairs of the integrated circuits involves laser scribing, without the use of a mask layer, the passivation layer to provide scribe lines exposing the semiconductor wafer. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, wherein the passivation layer protects the integrated circuits during at least a portion of the plasma etching. The method also involves thinning the passivation layer to partially expose the metal pillar/solder bump pairs of the integrated circuits.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: December 8, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, James S. Papanu, Ajay Kumar
  • Patent number: 9196536
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a phase modulated laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: November 24, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Jungrae Park, Wei-Sheng Lei, James S. Papanu, Brad Eaton, Ajay Kumar
  • Publication number: 20150332970
    Abstract: Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a carrier for supporting a wafer or substrate in an etch process includes a frame having a perimeter surrounding an inner opening. The frame is composed of a thermally resistant material. The carrier also includes a carrier tape coupled to the frame and disposed at least within the inner opening of the frame. The carrier tape includes a base film.
    Type: Application
    Filed: May 15, 2015
    Publication date: November 19, 2015
    Inventors: Wei-Sheng Lei, Brad Eaton, Ajay Kumar
  • Patent number: 9177864
    Abstract: Methods of using a hybrid mask composed of a first water soluble film layer and a second water-soluble layer for wafer dicing using laser scribing and plasma etch described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a hybrid mask above the semiconductor wafer. The hybrid mask is composed of a first water-soluble layer disposed on the integrated circuits, and a second water-soluble layer disposed on the first water-soluble layer. The method also involves patterning the hybrid mask with a laser scribing process to provide a patterned hybrid mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also involves etching the semiconductor wafer through the gaps in the patterned hybrid mask to singulate the integrated circuits.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: November 3, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Aparna Iyer, Todd Egan, Madhava Rao Yalamanchili, Ajay Kumar
  • Patent number: 9177861
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an elliptical or a spatio-temporal controlled laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: November 3, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Jungrae Park, Wei-Sheng Lei, James S. Papanu, Brad Eaton, Ajay Kumar
  • Publication number: 20150311118
    Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of scribing a semiconductor wafer having a plurality of integrated circuits involves adhering a backside of a semiconductor wafer to an inner portion of a carrier tape of a substrate carrier that includes a tape frame mounted above the carrier tape. The method also involves overlaying a protective frame above a front side of the semiconductor wafer and above an exposed outer portion of the carrier tape, the protective frame having an opening exposing an inner region of the front side of the semiconductor wafer. The method also involves laser scribing the front side of the semiconductor wafer with the protective frame in place.
    Type: Application
    Filed: May 7, 2014
    Publication date: October 29, 2015
    Inventors: Wei-Sheng Lei, Brad Eaton, Ajay Kumar
  • Publication number: 20150311107
    Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of reducing edge warping in a supported semiconductor wafer involves adhering a backside of a semiconductor wafer to an inner portion of a carrier tape of a substrate carrier comprising a tape frame mounted above the carrier tape. The method also involves adhering an adhesive tape to a front side of the semiconductor wafer and to at least a portion of the substrate carrier. The adhesive tape includes an opening exposing an inner region of the front side of the semiconductor wafer.
    Type: Application
    Filed: November 14, 2014
    Publication date: October 29, 2015
    Inventors: Wei-Sheng Lei, Brad Eaton, Ajay Kumar
  • Publication number: 20150303111
    Abstract: Approaches for hybrid laser scribe and plasma etch dicing process for a wafer having backside solder bumps are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof and corresponding arrays of metal bumps on a backside thereof involves applying a dicing tape to the backside of the semiconductor wafer, the dicing tape covering the arrays of metal bumps. The method also involves, subsequently, forming a mask on the front side of the semiconductor wafer, the mask covering the integrated circuits. The method also involves forming scribe lines on the front side of the semiconductor wafer with a laser scribing process, the scribe lines formed in the mask and between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, the mask protecting the integrated circuits during the plasma etching.
    Type: Application
    Filed: November 17, 2014
    Publication date: October 22, 2015
    Inventors: Wei-Sheng Lei, James S. Papanu, Aparna Iyer, Brad Eaton, Ajay Kumar
  • Patent number: 9165832
    Abstract: A method and system of hybrid laser dicing are described. In one embodiment, a method includes focusing a laser beam inside a substrate in regions between integrated circuits, inducing defects inside the substrate in the regions. The method involves patterning a surface of the substrate with a laser scribing process in the regions after inducing the defects in the substrate. The method further involves singulating the integrated circuits at the regions with the induced defects. In another embodiment, a system includes a first laser module configured to focus a laser beam inside a substrate in regions between integrated circuits, inducing defects inside the substrate in the regions. A second laser module is configured to pattern a surface of the substrate with a laser scribing process in the regions after inducing the defects. A tape extender is configured to stretch tape over which the substrate is mounted, singulating the integrated circuits.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: October 20, 2015
    Assignee: Applied Materials, Inc.
    Inventors: James S. Papanu, Wei-Sheng Lei, Jungrae Park, Alexander Lerner, Brad Eaton, Ajay Kumar
  • Publication number: 20150294892
    Abstract: Methods and systems for forming water soluble masks by dry film lamination are described. Also described are methods of wafer dicing, including formation of a water soluble mask by dry film lamination. In one embodiment, a method involves moisturizing an inner area of a water soluble dry film. The method involves stretching the water soluble dry film over a surface of the semiconductor wafer, and attaching the moistened inner area of the stretched film to the surface of the semiconductor wafer. A method of wafer dicing may further involve patterning the water soluble dry film, exposing regions of the semiconductor wafer between the ICs, and etching the semiconductor wafer through gaps in the patterned water soluble dry film.
    Type: Application
    Filed: December 8, 2014
    Publication date: October 15, 2015
    Inventors: Wei-Sheng Lei, James S. Papanu, Brad Eaton, Ajay Kumar
  • Patent number: 9159621
    Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of scribing a semiconductor wafer having a plurality of integrated circuits involves adhering a backside of a semiconductor wafer to an inner portion of a carrier tape of a substrate carrier that includes a tape frame mounted above the carrier tape. The method also involves overlaying a protective frame above a front side of the semiconductor wafer and above an exposed outer portion of the carrier tape, the protective frame having an opening exposing an inner region of the front side of the semiconductor wafer. The method also involves laser scribing the front side of the semiconductor wafer with the protective frame in place.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: October 13, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Ajay Kumar
  • Patent number: 9159624
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves laminating a polymeric mask layer onto a front side of the semiconductor wafer by dry film vacuum lamination, the polymeric mask layer covering and protecting the integrated circuits. The method also involves patterning the polymeric mask layer with a laser scribing process to provide gaps in the polymeric mask layer, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the gaps in the polymeric mask layer to singulate the integrated circuits. The method also involves, subsequent to plasma etching the semiconductor wafer, removing the polymeric mask layer.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: October 13, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Prabhat Kumar, James S. Papanu, Brad Eaton, Ajay Kumar
  • Publication number: 20150287638
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a collimated laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Application
    Filed: April 8, 2014
    Publication date: October 8, 2015
    Inventors: Jungrae Park, Wei-Sheng Lei, James S. Papanu, Brad Eaton, Ajay Kumar
  • Publication number: 20150279739
    Abstract: Approaches for front side laser scribe plus backside bump formation and laser scribe and plasma etch dicing process are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof involves forming first scribe lines on the front side, between the integrated circuits, with a first laser scribing process. The method also involves forming arrays of metal bumps on a backside of the semiconductor wafer, each array corresponding to one of the integrated circuits. The method also involves forming second scribe lines on the backside, between the arrays of metal bumps, with a second laser scribing process, wherein the second scribe lines are aligned with the first scribe lines. The method also involves plasma etching the semiconductor wafer through the second scribe lines to singulate the integrated circuits.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 1, 2015
    Inventors: Wei-Sheng Lei, James S. Papanu, Aparna Iyer, Brad Eaton, Ajay Kumar
  • Patent number: 9142459
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves applying an adhesive layer to a front side of the semiconductor wafer. A mask layer is laminated onto the front side of the semiconductor wafer, the mask layer covering and protecting the integrated circuits. The adhesive layer adheres the mask layer to the front side of the semiconductor wafer. The mask layer is patterned with a laser scribing process to provide gaps in the mask layer, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the mask layer to singulate the integrated circuits.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: September 22, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Prabhat Kumar, Wei-Sheng Lei, Brad Eaton, Ajay Kumar
  • Publication number: 20150255346
    Abstract: Baking methods and tools for improved wafer coating are described. In one embodiment, a method of dicing a semiconductor wafer including integrated circuits involves coating a surface of the semiconductor wafer to form a mask covering the integrated circuits. The method involves baking the mask with radiation from one or more light sources. The method involves patterning the mask with a laser scribing process to provide a patterned mask with gaps, exposing regions of the substrate between the ICs. The method may also involves singulating the ICs, such as with a plasma etching operation.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 10, 2015
    Inventors: Jungrae PARK, Wei-Sheng LEI, James S. PAPANU, Brad EATON, Ajay KUMAR
  • Patent number: 9130056
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof involves laminating a pre-patterned bi-layer wafer-level underfill material stack on the integrated circuits of the semiconductor wafer. The pre-patterned bi-layer wafer-level underfill material stack has regions corresponding to the integrated circuits and gaps corresponding to dicing streets between the integrated circuits. The method also involves plasma etching to form trenches in the semiconductor wafer in alignment with the dicing streets to singulate the integrated circuits. An upper layer of the pre-patterned bi-layer wafer-level underfill material stack protects the integrated circuits during the plasma etching.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: September 8, 2015
    Assignee: Applied Materials, Inc.
    Inventors: James M. Holden, James S. Papanu, Wei-Sheng Lei, Brad Eaton, Ajay Kumar