Abstract: According to the embodiment of the present invention, a semiconductor device includes a first nanodevice and a second nanodevice. The second nanodevice is located adjacent to and parallel to the first nanodevice along a first axis. The first nanodevice and the second nanodevice each include a first section, a second section, and a third section. A first gate cut region is located between the first sections of the first nanodevice and the second nanodevice. A middle gate cut region is located between the second sections of the first nanodevice and the second nanodevice. A third gate cut region is located between the third sections of the first nanodevice and the second nanodevice. The middle gate cut region has different dimensions along a second axis than the first gate cut region and the third gate cut region. A middle section contact is located in the middle gate cut region.

Abstract: A semiconductor device that includes a first via connecting a backside of the semiconductor device to a frontside of the semiconductor device, and a second via connecting the backside of the semiconductor device to the frontside of the semiconductor device. The first via and the second via are directly connected to at least one different wiring level on the frontside or the backside.

Abstract: A semiconductor device having a source/drain having a height, a length, and a width. A full wrap-around contact surrounds a partial length of the source/drain. The full wrap-around contact includes a frontside recessed wrap-around contact from a front side of the source/drain and a backside conductive contact from a back side of the source/drain.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, and a pFET transistor formed on the semiconductor substrate. The pFET transistor includes a plurality of channel regions. An uppermost channel region of the plurality of channel regions includes an uppermost active semiconductor layer and a capping layer formed on the uppermost active semiconductor layer.

Abstract: A medical device includes wake circuitry and telemetry circuitry. The wake circuitry is configured to receive a first set of data from a device associated with the medical device, where the first set of data is received at a frequency band. The wake circuitry is configured to output a set of pulses based on the first set of data. The wake circuitry is configured to detect a data pattern using the set of pulses. The wake circuitry is configured to output an activation signal in response to a determination that the data pattern satisfies a data pattern requirement. The telemetry circuitry is configured to output a second set of data in response to receiving the activation signal. The second set of data is transmitted at the frequency band. The telemetry circuitry is configured to establish a communication session with the device using the second set of data.

Abstract: A semiconductor structure having improved performance is provided that includes a local enlarged via-to-backside power rail (VBPR) contact structure which connects a source/drain region of one field effect transistor (FET) to a backside power rail.

Abstract: A semiconductor structure comprises a vertical transistor, a first contact connecting to a source/drain region at a first side of the vertical transistor, a second contact extending from the first side of the vertical transistor to a second side of the vertical transistor, and an interconnect structure at the first side of the vertical transistor connecting the first contact to the second contact.

Abstract: A semiconductor structure including a fin of a vertical transistor structure, a top source drain region on a top side of the fin, a bottom source drain region on a bottom side of the fin, and a backside contact below and contacting the bottom source drain region.

Abstract: Embodiments of the invention include a transistor comprising a gate region and an epitaxial region, the transistor comprising a frontside opposite a backside.

Abstract: A field effect transistor (FET) cell structure of an integrated circuit (IC) is provided. The FET cell structure includes first and second adjacent cells. Each of the first and second adjacent cells spans a first layer and a second layer. The second layer is vertically stacked on the first layer. The first cell includes n-doped FETs (NFETs) on one of the first and second layers and p-doped FETs (PFETs) on another of the first and second layers. The second cell includes at least one of a number of NFETs on the one of the first and second layers differing from a number of the NFETs in the first cell and a number of PFETs on the another of the first and second layers differing from a number of the PFETs in the first cell.

Abstract: A semiconductor apparatus includes a substrate; a first conductive feature disposed on the substrate, the first conductive feature comprising a conductive material; a second conductive feature disposed on the substrate, the second conductive feature comprising the conductive material; a dielectric material at least partially surrounding the first conductive feature and the second conductive feature; and an interconnect between the first conductive feature and the second conductive feature, the interconnect comprising the conductive material integral with the first conductive feature and the second conductive feature and extending through the dielectric material and below the first conductive feature and the second conductive feature.

Abstract: A semiconductor structure includes a first stacked device structure. The first stacked device structure includes a first field-effect transistor disposed on a substrate having a front side and a back side. The first field-effect transistor has a first source/drain region. The first stacked device structure further includes a second field-effect transistor vertically stacked above the first field-effect transistor. The second field-effect transistor has a second source/drain region. The first stacked device structure further includes a first front side source/drain contact disposed on the first source/drain region and a first back side source/drain contact disposed on the second source/drain region. The first stacked device structure further includes a first isolation pillar structure located within the first field-effect transistor, the second field-effect transistor, the first front side source/drain contact and the first back side source/drain contact.

Abstract: A semiconductor device includes a first vertical field-effect transistor comprising a first set of vertical fins and a second set of vertical fins separated by a first isolation pillar structure. The semiconductor device further includes a second vertical field-effect transistor adjacent to the first vertical field-effect transistor, the second vertical field-effect transistor comprising a first set of vertical fins and a second set of vertical fins separated by a second isolation pillar structure.

Abstract: An integrated circuit (IC) assembly method is provided. The method includes fabricating a first wafer including a first device with a back end of line (BEOL) and first terminals of first and second types at the BEOL and fabricating a second wafer including a second device for back side power delivery network (BSPDN) processing, second terminals of the first type, first vias and second vias. The first and second wafers are bonded at the BEOL to connect the second terminals of the first type to a subset of the first terminals of the first type, the first vias to remaining first terminals of the first type, and the second vias to the first terminals of the second type. A BSPDN is built onto a backside of the second wafer to include first and second BSPDN terminals connected to the first and second vias, respectively.

Abstract: A semiconductor structure is provided that includes a first pair of stacked devices located in a first active device region and a second pair of stacked devices located in a second active device region. Each stacked device of the pair of stacked devices includes a second field effect transistor (FET) stacked over a first FET, and within each active device region the pair of stacked devices is separated by an inter-device dielectric pillar. A local interconnect structure is located in a non-active device region that is positioned between the first and second active device regions. The local interconnect structure can be connected to a back side power rail and a source/drain region of one of the second FETs, or connected to a front side signal line and a source/drain region of one of the first FETs.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a first trench partially through a first substrate from a first side of the first substrate. The method also includes widening a bottom portion of the first trench to form a lateral footing area of the first trench. The method includes forming a first metallization in the first trench; forming a second trench through a second substrate from a second side of the second substrate to expose at least a portion of first metallization in an area corresponding to the lateral footing area of the first trench, the second side being opposite to the first side. The method also includes forming a second metallization in the second trench in contact with the first metallization.

Abstract: An approach forming semiconductor structure composed of a first plurality of vertical transport field-effect transistors in a lower semiconductor layer and a second plurality of vertical transport field-effect transistors in an upper semiconductor layer. The second plurality of vertical transport field-effect transistors is horizontally offset from the first plurality of vertical transport field-effect transistors by a horizontal distance that is one-half of a contacted gate pitch between adjacent vertical transport field-effect transistors in the same semiconductor layer.

Abstract: A backside power distribution network is provided having an integrated signal line with a backside connection to a transistor gate. In one aspect, a semiconductor device includes: NFETs and PFETs adjacent to one another on a frontside of a wafer; power rails, connected to source/drain regions of the NFETs and PFETs, present on a backside of the wafer in a space between adjacent NFETs and in a space between adjacent PFETs; and a signal line, connected to a gate of the NFETs and PFETs, present on the backside of the wafer in a space between an adjacent NFET and PFET. The NFETs and PFETs can each include a stack of active layers, and gates surrounding at least a portion of each of the active layers in a gate-all-around configuration. A method of fabricating the present semiconductor devices is provided.

Abstract: A microelectronic structure including a static random-access memory (SRAM) device that includes a plurality of stacked transistors. Each of the plurality of stacked transistors that includes a bottom transistor and an upper transistor, where the upper transistor is not in vertical alignment with the bottom transistor.

Abstract: A back side contact structure is provided that directly connects a first electrode of a MRAM, which is present in a back side of a wafer, to a source/drain structure of a transistor. The back side contact is self-aligned to the source/drain structure of the transistor as well as to the first electrode of the MRAM. The close proximity between the MRAM and the source/drain structure increases the speed of the device. MRAM yield is not compromised since no re-sputtering of back side contact metal onto the MRAM occurs.