Abstract: A semiconductor device containing a self-aligned contact rail is provided. The self-aligned contact rail can have a reduced critical dimension, CD. The self-aligned contact rail can be obtained utilizing a sacrificial semiconductor fin as a placeholder structure for the contact rail. The used of the sacrificial semiconductor fin enables reduced, and more controllable, CDs.

Abstract: Interconnect designs with reduced via resistance are provided. In one aspect, an interconnect structure includes: at least a first metal line and a second metal line; and a conductive via in between the first metal line and the second metal line, wherein the conductive via has elongated dimensions along a major axis of the first metal line and along a major axis of the second metal line. Dielectric caps can be present on the first metal lines, and below and above the second metal lines. A method of forming the present interconnect structure is also provided.

Abstract: A method of forming a top via is provided. The method includes forming a sacrificial trench layer and conductive trench plug in an interlayer dielectric (ILD) layer on a conductive line. The method further includes forming a cover layer on the ILD layer, sacrificial trench layer, and conductive trench plug, and forming a sacrificial channel layer and a conductive channel plug on the conductive trench plug. The method further includes removing the cover layer and the ILD layer to expose the sacrificial trench layer and the sacrificial channel layer. The method further includes removing the sacrificial trench layer and the sacrificial channel layer, and forming a barrier layer on the conductive channel plug and conductive trench plug.

Abstract: A microelectronic structure comprises a first interconnect line at a first interconnect level, a second interconnect line at a second interconnect level, and at least one via connecting the first interconnect line at the first interconnect level to the second interconnect line at the second interconnect level. The at least one via comprises a vertical section and at least one horizontal section, the at least one horizontal section being in contact with at least a portion of one of a top surface of the first interconnect line and a bottom surface of the second interconnect line.

Abstract: An approach providing a semiconductor wiring structure with a self-aligned top via on a first metal line and under a second metal line. The semiconductor wiring structure includes a plurality of first metal lines in a bottom portion of a first dielectric material. The semiconductor wiring structure includes a top via in a top portion of the first dielectric material, where the top via is over a first metal line of the plurality of first metal lines. The semiconductor wiring structure includes a second dielectric material above each of the plurality of first metal lines except the first metal line of the plurality of first metal lines. Furthermore, the semiconductor wiring structure includes a second metal line above the top via, wherein the second metal line is in a third dielectric material and a hardmask layer that is under the third dielectric material.

Abstract: A semiconductor device is provided that includes at least one stacked FET device including two top transistors stacked over a single bottom transistor. The at least one stacked FET includes a full gate cut structure that is used to separate different device areas from each other, a top gate cut structure that used to separate the two top transistors, and a bottom gate cut structure that is used to provide the single bottom transistor. The at least one FET device can be used to provide a SRAM containing six transistors.

Abstract: Provided is a semiconductor device. The semiconductor device comprises a plurality of logic devices. The logic devices have frontside wiring. The semiconductor device further comprises a backside power delivery network (BSPDN). The semiconductor device further comprises a connection between the BSPDN and the bottom of a source/drain epitaxy of a logic device. The connection is self-aligned on at least two sides.

Abstract: A plurality of transistor components, a system, and a method of forming a vertically stacked transistor structure within a wafer. The plurality of transistor components may include a first bottom transistor, where the first bottom transistor includes a channel, a gate, a source, and a drain. The plurality of transistor components may also include a first contact on top of the first bottom transistor, where the first contact is proximately connected to the first bottom transistor. The plurality of transistor components may also include a first set of stacked transistors, where the first set of stacked transistors includes a second top transistor on top of a second bottom transistor.

Abstract: A field effect transistor (“FET”) stack, including a lower FET, and an upper FET, a first contact to a lower source drain of the lower FET, a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain, a first overlap region between the first silicide and the first contact is less than a second overlap region between the first silicide and the first source drain. The first contact has a reverse tapper metal stud profile. Forming a first contact to a lower source drain of a lower FET of an FET stack, forming a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain.

Abstract: A semiconductor device is provided. The semiconductor device includes a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions. The semiconductor device also includes a gate cut region at cell boundaries between the first and second S/D epitaxial regions, a dielectric liner and a dielectric core formed in the gate cut region, and a backside power rail (BPR) and a backside power distribution network (BSPDN). The semiconductor device also includes a power via passing through the dielectric core and connecting to the BPR and BSPDN, first metal contacts formed in contact with the first and second S/D epitaxial regions, and a via to backside power rail (VBPR) contact. The dielectric liner separates the power via from the first S/D epitaxial region.

Abstract: Embodiments are disclosed for a complementary metal oxide semiconductor (CMOS) device. The CMOS device includes a hybrid cross-couple contact. The hybrid cross-couple contact includes a frontside contact to a gate of the CMOS device. The frontside contact is disposed on a frontside of the CMOS device. The hybrid cross-couple contact includes a source contact to a source of the CMOS device. The source contact is disposed on a backside of the CMOS device. The hybrid cross-couple contact includes a drain contact to a drain of the CMOS device. The drain contact is disposed on a backside of the CMOS device.

Abstract: An apparatus includes a fin, a gate, and a gate contact. A portion of the fin is disposed in a first layer. The gate is disposed in the first layer and adjacent to the fin. The gate contact is disposed on the gate and in a second layer, wherein the second layer is disposed on the first layer such that the gate contact is above the fin.

Abstract: A microelectronic structure including a plurality of lower transistors and a plurality of upper transistors, where channels of the upper transistors are staggered from channels of the lower transistors. A lower dielectric pillar located beneath an upper transistor, where the dielectric pillar separates bottom transistors.

Abstract: A heat pipe is provided as an electrically inactive structure to dissipate heat that is generated by vertically stacked field effect transistors (FETs). The heat pipe is present in an electrically inactive device area which is located adjacent to an electrically active device area that includes the vertically stacked FETs.

Abstract: A microelectronic structure including a plurality of lower transistors and a plurality of upper transistor, where each of the plurality of lower transistors and the plurality of upper transistors includes a plurality of channel. Where an upper center vertical axis of each of the plurality of upper transistors is staggered from a lower center vertical axis of each of the lower transistors. A lower gate cut is located between each of the plurality of lower transistors. A first upper gate cut located adjacent to a first upper transistor of the plurality of upper transistors, where the first upper gate cut is in direct contact with a plurality of first channels of the first upper transistor.

Abstract: A semiconductor device is provided. The semiconductor device includes a bottom field effect transistor (FET) including a bottom source-drain epitaxial layer formed on sides of the bottom FET; a top FET stacked over the bottom FET; a back-end-of-line (BEOL) layer formed on the top FET; a bottom gate contact formed in contact with the bottom FET and having an extending portion of the bottom gate contact that extends laterally over the bottom source-drain epitaxial layer; and a top gate contact formed in contact with the extending portion of the bottom gate contact and electrically connecting the bottom gate contact to the BEOL layer.

Abstract: An approach to provide a semiconductor structure using different two metal materials for interconnects in the middle of the line and the back end of the line metal layers of a semiconductor chip. The semiconductor structure includes the first metal material connecting both horizontally and vertically with the second metal material and the second metal material connecting both horizontally and vertically with the first metal material where the second metal material is more resistant to electromigration than the first metal material.

Abstract: A semiconductor device is provided. The semiconductor device includes a buried power rail, a buried oxide (BOX) layer formed on the buried power rail, a plurality of channel fins formed on the BOX layer, a bottom epitaxial layer formed on the BOX layer and between the channel fins such that the BOX layer is between the buried power rail and the bottom epitaxial layer, a gate stack formed over the bottom epitaxial layer and contacting the channel fins, the gate stack including a work function metal (WFM) layer and a high-x layer, and a top epitaxial layer formed on the gate stack. In the semiconductor device, between two adjacent ones of the channel fins the BOX layer has an opening so that the bottom epitaxial layer is electrically connected to the buried power rail.

Abstract: A microelectronic structure including a stacked device region, where stacked device region is comprised of a plurality of top devices and a plurality of bottom devices. Each of the plurality of top devices includes at least one top source/drain. Each of the plurality of bottom devices includes at least one bottom source/drain. A gate cut region located adjacent to the stacked region and an interconnect located in the gate cut region. The interconnect is connected to at least two different devices located in the stacked device region.

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures that provide buried contacts in the fin-to-fin space of vertical transport field effect transistors (VFETs) that connect the bottom S/D of the transistors to a buried power rail. In a non-limiting embodiment of the invention, a buried power rail is encapsulated in a buried oxide layer of a first wafer. First and second semiconductor fins are formed on a second wafer. The first wafer to the second wafer and a surface of the buried power rail in a fin-to-fin space is exposed. A buried via is formed on the exposed surface of the buried power rail. The buried via electrically couples the buried power rail to a bottom source or drain region of the first semiconductor fin.