Abstract: A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and bottom side. Active regions are disposed on the bottom side. The active regions include a recessed portion therein. A metal cap is disposed within the recessed portion. A contact is disposed within the metal cap to reduce contact resistance.

Abstract: A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and a bottom side. Active regions are disposed on the bottom side including a leveled surface facing the top side and a faceted backside surface opposite the leveled surface. The leveled surface includes two different semiconductor materials. A backside contact in contact with the faceted backside surface forms a wraparound contact to reduce contact resistance.

Abstract: A semiconductor device architecture includes a substrate and a device region including active components carried by the substrate. A plurality of tracks are on the substrate including conductive lines connecting power and signals to the active components in the device region. A first track includes a plurality of segments of a conductive line. A first segment in the first track delivers power to the device region. A second segment in the first track delivers a signal to the device region. The first segment and the second segment are arranged in the same first track.

Abstract: Disclosed is an illumination device for use with spoked wheels, such as bicycle wheels, wherein the wheel includes a hub portion, a plurality of spokes, and a rim portion. The illumination device includes a power pack, at least one adaptor body, and at least one attachment portion. The power pack having at least one wire, a flexible button cap, a body housing, and circuit board with a switch. The at least one wire including a plurality of light sources. The at least one attachment portion including a clip portion providing for the installation of the at least one adaptor body to the bicycle spokes. The illumination device also includes a holder for the installation of the power pack to the bicycle wheel. Further, the illumination device may include a tubular body located in the internal cavity of the at least one adaptor body.

Abstract: A semiconductor device includes a plurality of gate caps over a plurality of gate regions, gate spacers over sidewalls of the plurality of gate regions and the plurality of gate caps, a backside contact under a first source and drain region and a dielectric cap over the first source and drain region. The first source and drain region is located between two adjacent gate regions of the plurality of gate regions.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first transistor having a first source/drain (S/D) region; a second transistor having a second S/D region, the second transistor being stacked on top of the first transistor; and a first S/D contact shared by the first S/D region of the first transistor and the second S/D region of the second transistor, where the first S/D contact has a first portion and a second portion, the first portion being in direct contact with a top surface of the first S/D region of the first transistor and in direct contact with a bottom surface of the second S/D region, and the second portion being in direct contact with an inner sidewall of the second S/D region of the second transistor. A method of manufacturing the semiconductor structure is also provided.

Abstract: A head-mounted display may include a display system and an optical system in a housing. The display system may have a pixel array that produces light associated with images. The display system may also have a linear polarizer through which light from the pixel array passes and a quarter wave plate through which the light passes after passing through the quarter wave plate. The optical system may be a catadioptric optical system having one or more lens elements. The lens elements may include a plano-convex lens and a plano-concave lens. A partially reflective mirror may be formed on a convex surface of the plano-convex lens. A reflective polarizer may be formed on the planar surface of the plano-convex lens or the concave surface of the plano-concave lens. An additional quarter wave plate may be located between the reflective polarizer and the partially reflective mirror.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a device layer having a frontside and a backside and including a transistor that includes a source/drain region at the backside of the device layer; a first and a second backside metal line with the source/drain region at least partially overlapping vertically with the first backside metal line and not overlapping vertically with the second backside metal line; and a backside local interconnect that conductively connects the source/drain region of the transistor with the second backside metal line, where the backside local interconnect includes a first portion and a second portion, the first portion horizontally extending from an area underneath the source/drain region to an area outside the source/drain region of the transistor, the second portion vertically connecting the first portion to the second backside metal line. Methods for forming the same are also provided.

Abstract: A semiconductor device comprises a top field effect transistor (FET) and a bottom FET in a stacked profile. The semiconductor device also comprises a gate. The gate comprises two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises an insulator liner. The insulator liner interfaces with the two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises a dielectric that interfaces with the insulator liner.

Abstract: A semiconductor structure including a device layer, a back end-of-line layer, and a backside power distribution layer. The backside power distribution layer includes a first line network with having a first pitch, and a second line network having a second pitch. The second pitch is greater than the first pitch. In one example, the second pitch is at least 7 times (7×) greater than the first pitch.

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the semiconductor substrate; an active device layer at a top side of the plurality of first dielectric layers; and a plurality of second dielectric layers at a top side of the active device layer. Also included are at least hundreds of metal bodies, each of which is on the order of about 10 nm to about 1000 nm in critical dimension and includes: a first metal plate, at a first level in the plurality of first dielectric layers that is adjacent to the active device layer; a second metal plate, at a second level in the plurality of second dielectric layers that is adjacent to the active device layer; and a first plurality of vias that connect the first metal plate to the second metal plate through the active device layer.

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first layers; a plurality of second dielectric layers at a top side of the device layer; first and second sense pads; and a metal body that electrically connects the pads. The metal body includes a first portion that is embedded in the first layers, made of a first plurality of discrete segments; a second portion that is embedded in the second layers, made of a second plurality of discrete segments, of which a first is electrically connected to the first pad and a second is electrically connected to the second pad; and a plurality of vias that interconnect the first and second portions. Breaking any of the vias reduces the electrical connectivity between the pads.

Abstract: An exemplary structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first dielectric layers; a plurality of second dielectric layers at a top side of the active device layer; and a metal body. The body includes a first portion that is embedded in the plurality of first dielectric layers. The first portion comprises a first layer of first metal. The body further includes a second portion that is embedded in the plurality of second dielectric layers. The second portion comprises a first layer of second metal. A plurality of vias interconnect the first portion to the second portion through the active device layer. The first layer of the first portion mechanically connects the plurality of vias and the first layer of the second portion mechanically connects the plurality of vias.

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first layers; a plurality of second dielectric layers at a top side of the device layer; first and second sense pads at a top side of the second layers; a first metal body electrically connected to the first pad; and a second metal body electrically connected to the second pad. The bodies, with the layers, form a capacitor that couples the pads. Each of the bodies includes: an upper portion that is embedded in the plurality of second layers and is directly connected to a respective one of the first and second pads; a lower portion that is embedded in the plurality of first layers; and a via that connects the upper to the lower portion through the active layer.

Abstract: A structure comprising: metal lines and viabars that surround a periphery of an active area of a semiconductor device; at least one viabar that extends through multiple layers of the semiconductor device, wherein the at least one viabar connects a metal line of one layer of the structure with a metal line of another layer of the structure; and a connection viabar that terminates at a metal line of a layer between the one layer of the structure and the another layer of the structure, wherein a thickness of the connection viabar is less than a thickness of the at least one viabar.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor device comprising: a back end of the line (BEOL) stack including a dielectric stack, and an active device region in the dielectric stack, the active device region including at least one component selected from the group consisting of transistors, capacitors and nanosheet structures; and a crack stop that extends vertically through the active device region.

Abstract: A semiconductor structure with two adjacent semiconductor devices of a plurality of semiconductor devices that have a backside contact that connects two adjacent source/drains of the two adjacent semiconductor devices to a backside power rail. The semiconductor provides the backside contact with a larger bottom contact area with the backside power rail than a combined contact area of the two top surfaces of the backside contact with the two adjacent source/drains.

Abstract: A semiconductor structure includes a first set of transistors in a first level, the first set of transistors having a first gate pitch and a first cell height, and a second set of transistors in a second level, the second set of transistors having a second gate pitch and a second cell height. The second level is vertically stacked over the first level, the first gate pitch is different than the second gate pitch, and the first cell height is different than the second cell height.

Abstract: A semiconductor IC device includes an inverted gate cut region with a relatively larger bottom surface area compared to its top surface area. As a result, an associated gate structure may have a relatively larger top contact landing surface area relative to its bottom surface area. The increased landing area further enables the frontside contact to be in further perimeter locations. The inverted gate cut region also results in improved resistance characteristics through the gate structure. Specifically, the inverted gate cut region enables a wide region between a top channel and the inverted gate cut region that provides a relatively lower electrical resistance therethrough. Similarly, the inverted gate cut region causes a bottom perimeter region with decreased conductive material therein which advantageously results in lower associated parasitic capacitances.

Abstract: A semiconductor structure with a first backside metal level that has a plurality of first type of lines and at least one second type line. The first type of lines have a wider top surface than the bottom surface and have a first width. The first type of lines each connect by a first via to a second backside metal level. Each of first type of lines and the second type line connect by a second via to a through-silicon via. The second type line is narrower than the first type of lines. Each of the second type line is between adjacent first type of lines. The second type line has a top surface that is in the middle of the first type of lines, below the first type of lines, above, or level with the top surface of the first type of lines.