Patents by Inventor Brent Anderson

Brent Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250113560
    Abstract: A semiconductor structure, system, and method of forming a crescent-shaped dielectric isolation layer for stacked field-effect transistors (FETs). The semiconductor structure may include a transistor including an epi. The semiconductor may also include a substrate, where the epi is directly connected to the substrate. The semiconductor may also include an isolation layer directly connected to the epi and the substrate. The system may include a semiconductor structure. The method may include forming an isolation layer directly connected to a substrate. The method may also include forming a first transistor, where forming the first transistor includes growing a first epi, where the first epi is directly connected to the isolation layer and the substrate.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Lijuan Zou, Jay William Strane, Junli Wang, Brent A. Anderson, Ruilong Xie, Albert M. Chu
  • Publication number: 20250112121
    Abstract: A semiconductor device includes a prime active region and a barrier region within the active prime region to define a barrier across a depth of the active prime region. A bypass structure includes a contact connecting to a component within the active prime region and extending outside the active prime region, a metal layer connecting to the first contact outside the active prime region and a through via passing through the depth of the active prime region and connecting to a solder bump.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Inventors: Nicholas Alexander POLOMOFF, Brent A. Anderson, Lawrence A. Clevenger, Ruilong Xie
  • Patent number: 12268026
    Abstract: A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: April 1, 2025
    Assignee: International Business Machines Corporation
    Inventors: Junli Wang, Brent A Anderson, Terence Hook, Indira Seshadri, Albert M. Young, Stuart Sieg, Su Chen Fan, Shogo Mochizuki
  • Patent number: 12268031
    Abstract: A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: April 1, 2025
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Kisik Choi, Somnath Ghosh, Sagarika Mukesh, Albert Chu, Albert M. Young, Balasubramanian S. Pranatharthiharan, Huiming Bu, Kai Zhao, John Christopher Arnold, Brent A. Anderson, Dechao Guo
  • Patent number: 12268016
    Abstract: A channel fin extends vertically above a bottom source/drain region, a protective liner is positioned along opposite sidewalls of the bottom source/drain region. The bottom source/drain region is positioned above a semiconductor layer in contact with a first portion of an inner spacer. A first metal layer is positioned between the first portion of the inner spacer and a second portion of the inner spacer, the first portion of the inner spacer partially covers a top surface of the first metal layer and the second portion of the inner spacer substantially covers a bottom surface of the first metal layer for providing a buried power rail. A shallow trench isolation region is positioned above an exposed portion of the first metal layer, the shallow trench isolation region is adjacent to the first portion of the inner spacer, the semiconductor layer, and the bottom source/drain region.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: April 1, 2025
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Junli Wang, Brent A Anderson, Chen Zhang, Heng Wu, Alexander Reznicek
  • Publication number: 20250107205
    Abstract: A semiconductor device is provided. The semiconductor device includes an active region, a gate, a gate contact formed on the gate, the gate contact overlapping in plan view with at least a portion of the active region, and a source/drain contact formed on the active region and adjacent to the gate contact. The gate contact is offset from a centerline of the gate in a direction away from the source/drain contact.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 27, 2025
    Inventors: Albert M. Chu, Brent A. Anderson, Ravikumar Ramachandran
  • Publication number: 20250096132
    Abstract: Embodiments provide metal tip-to-tip scaling for metal contacts. A structure includes a first metal line and a second metal line. The structure includes a spacer separating the first metal line from the second metal line, the spacer including a flat surface and curved tips, where the flat surface abuts the first metal line and the curved tips abut the second metal line.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 20, 2025
    Inventors: Ruilong Xie, Brent A. Anderson, Nicholas Anthony Lanzillo, Lawrence A. Clevenger, Reinaldo Vega, Albert M. Chu
  • Publication number: 20250096074
    Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a front-end-of-line (FEOL) including a first source/drain (S/D) adjacent to a first gate. A device may include a backside interconnect below the FEOL, with a plurality of signal lines and a plurality of power lines. A device may include an offset gate contact electrically connected between the first gate and a first signal line of the plurality of signal lines, wherein the offset gate contact is located directly below the first S/D.
    Type: Application
    Filed: September 17, 2023
    Publication date: March 20, 2025
    Inventors: Ruilong Xie, Albert M Chu, Brent A. Anderson, Lawrence A. Clevenger
  • Publication number: 20250096126
    Abstract: A semiconductor integrated circuit (IC) device that includes a backside fuse structure. The backside fuse structure is located within the backside of the semiconductor IC device and may be vertically located between a microdevice and a backside back end of the line (BEOL) network. The backside fuse structure includes at least a fuse wire. The backside fuse structure may be in a non-programmed state or a programmed state. When in a non-programmed state, an open circuit exists that prevents current flow through the fuse wire. The backside fuse structure may be directly connected to a deep via contact and/or one or more conductive pathways within the backside BEOL network.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 20, 2025
    Inventors: Dan Moy, JENS HAETTY, Lawrence A. Clevenger, Xiaoming Yang, Brent A. Anderson, Ruilong Xie, Christopher Murphy
  • Publication number: 20250098288
    Abstract: A semiconductor integrated circuit (IC) device includes a backside resistor and a back end of the line (BEOL) network. The backside resistor is located upon a backside of the semiconductor IC device and may be vertically located between a front end of line (FEOL) microdevice, such as a diode and/or a transistor, and the BEOL network. The backside resistor is connected to the backside BEOL network and may be utilized to route current between different conductive pathways within the backside BEOL network or between the backside BEOL network and a frontside BEOL network.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 20, 2025
    Inventors: JENS HAETTY, Christopher Murphy, Lawrence A. Clevenger, Brent A. Anderson, Ruilong Xie
  • Publication number: 20250089336
    Abstract: A semiconductor device includes a top side and a bottom side opposite the top side. A central portion including a semiconductor substrate is disposed between the top side and the bottom side. A component is disposed in the central portion in contact with the semiconductor substrate. The component includes a first electrical connection from the top side and a second electrical connection from the bottom side.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Inventors: Brent A. Anderson, Albert M. Chu, Junli Wang, Ruilong Xie, Jay William Strane
  • Publication number: 20250081581
    Abstract: A semiconductor structure is provided that includes a self-aligned offset frontside gate contact structure and a direct backside source/drain contact structure. The presence of the off-centered frontside gate contact structure is attractive since it mitigates the risk of gate contact-to-source/drain contact shorts and it also improves the metal line, M1, spacing within the overlying frontside back-end-of-the-line (BEOL) structure.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 6, 2025
    Inventors: Ruilong Xie, Brent A. Anderson, Albert M. Chu, Ravikumar Ramachandran
  • Publication number: 20250062190
    Abstract: A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and a bottom side. Active regions are disposed on the bottom side including a leveled surface facing the top side and a faceted backside surface opposite the leveled surface. The leveled surface includes two different semiconductor materials. A backside contact in contact with the faceted backside surface forms a wraparound contact to reduce contact resistance.
    Type: Application
    Filed: August 18, 2023
    Publication date: February 20, 2025
    Inventors: Ruilong Xie, Jay William Strane, Shay Reboh, Brent A. Anderson, Junli Wang, Albert M. Chu
  • Publication number: 20250063795
    Abstract: A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and bottom side. Active regions are disposed on the bottom side. The active regions include a recessed portion therein. A metal cap is disposed within the recessed portion. A contact is disposed within the metal cap to reduce contact resistance.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 20, 2025
    Inventors: Ruilong Xie, Brent A. Anderson, Albert M. Chu, Junli Wang, Jay William Strane
  • Publication number: 20250050959
    Abstract: Disclosed is an illumination device for use with spoked wheels, such as bicycle wheels, wherein the wheel includes a hub portion, a plurality of spokes, and a rim portion. The illumination device includes a power pack, at least one adaptor body, and at least one attachment portion. The power pack having at least one wire, a flexible button cap, a body housing, and circuit board with a switch. The at least one wire including a plurality of light sources. The at least one attachment portion including a clip portion providing for the installation of the at least one adaptor body to the bicycle spokes. The illumination device also includes a holder for the installation of the power pack to the bicycle wheel. Further, the illumination device may include a tubular body located in the internal cavity of the at least one adaptor body.
    Type: Application
    Filed: October 23, 2024
    Publication date: February 13, 2025
    Applicant: Brightz, Ltd.
    Inventors: Brent ANDERSON, Brian FINCH
  • Publication number: 20250054863
    Abstract: A semiconductor device architecture includes a substrate and a device region including active components carried by the substrate. A plurality of tracks are on the substrate including conductive lines connecting power and signals to the active components in the device region. A first track includes a plurality of segments of a conductive line. A first segment in the first track delivers power to the device region. A second segment in the first track delivers a signal to the device region. The first segment and the second segment are arranged in the same first track.
    Type: Application
    Filed: August 12, 2023
    Publication date: February 13, 2025
    Inventors: Reinaldo Vega, Ruilong Xie, Nicholas Anthony Lanzillo, Albert M. Chu, Lawrence A. Clevenger, Brent A. Anderson, Takashi Ando, David Wolpert
  • Publication number: 20250040184
    Abstract: A semiconductor device includes a plurality of gate caps over a plurality of gate regions, gate spacers over sidewalls of the plurality of gate regions and the plurality of gate caps, a backside contact under a first source and drain region and a dielectric cap over the first source and drain region. The first source and drain region is located between two adjacent gate regions of the plurality of gate regions.
    Type: Application
    Filed: July 29, 2023
    Publication date: January 30, 2025
    Inventors: Ruilong Xie, Albert M. Chu, Brent A. Anderson, Lawrence A. Clevenger
  • Publication number: 20250040199
    Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first transistor having a first source/drain (S/D) region; a second transistor having a second S/D region, the second transistor being stacked on top of the first transistor; and a first S/D contact shared by the first S/D region of the first transistor and the second S/D region of the second transistor, where the first S/D contact has a first portion and a second portion, the first portion being in direct contact with a top surface of the first S/D region of the first transistor and in direct contact with a bottom surface of the second S/D region, and the second portion being in direct contact with an inner sidewall of the second S/D region of the second transistor. A method of manufacturing the semiconductor structure is also provided.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Inventors: Ruilong Xie, Brent A. Anderson, Albert M. Chu, Junli Wang, Jay William Strane
  • Publication number: 20250028158
    Abstract: A head-mounted display may include a display system and an optical system in a housing. The display system may have a pixel array that produces light associated with images. The display system may also have a linear polarizer through which light from the pixel array passes and a quarter wave plate through which the light passes after passing through the quarter wave plate. The optical system may be a catadioptric optical system having one or more lens elements. The lens elements may include a plano-convex lens and a plano-concave lens. A partially reflective mirror may be formed on a convex surface of the plano-convex lens. A reflective polarizer may be formed on the planar surface of the plano-convex lens or the concave surface of the plano-concave lens. An additional quarter wave plate may be located between the reflective polarizer and the partially reflective mirror.
    Type: Application
    Filed: October 2, 2024
    Publication date: January 23, 2025
    Inventors: Sajjad A. Khan, Nan Zhu, Graham B. Myhre, Brent J. Bollman, Tyler Anderson, Weibo Cheng, John N. Border
  • Publication number: 20250022795
    Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a device layer having a frontside and a backside and including a transistor that includes a source/drain region at the backside of the device layer; a first and a second backside metal line with the source/drain region at least partially overlapping vertically with the first backside metal line and not overlapping vertically with the second backside metal line; and a backside local interconnect that conductively connects the source/drain region of the transistor with the second backside metal line, where the backside local interconnect includes a first portion and a second portion, the first portion horizontally extending from an area underneath the source/drain region to an area outside the source/drain region of the transistor, the second portion vertically connecting the first portion to the second backside metal line. Methods for forming the same are also provided.
    Type: Application
    Filed: July 11, 2023
    Publication date: January 16, 2025
    Inventors: Nicholas Anthony Lanzillo, Lawrence A. Clevenger, Ruilong Xie, Reinaldo Vega, Albert M. Chu, Brent A. Anderson