Abstract: Embodiments of present invention provide a method of forming backside contact. The method includes forming a set of gate stacks on top of a substrate; forming a first recess in the substrate between the set of gate stacks, the first recess having a triangle shape with a pointy bottom; forming a dielectric anchor at the pointy bottom of the first recess; with the dielectric anchor at the pointy bottom, performing a sigma etch of the substrate through the first recess to form a second recess; epitaxially growing a semiconductor material in the second recess to form a placeholder for a backside contact; surrounding the placeholder with a dielectric material; and replacing the placeholder with a conductive material to form the backside contact. The semiconductor structure formed thereby is also provided.

Abstract: Embodiments disclosed herein describe semiconductor devices that include semiconductor structures and methods of forming the semiconductor structures. The semiconductor structures may include an upper conductive line, a first lower conductive line laterally insulated by a first lower dielectric region and a second lower dielectric region. The semiconductor structure also includes a lower level via region above the first lower conductive line. The lower level via region includes a dielectric blocking material and a spacer material.

Abstract: A head-mounted display may include a display system and an optical system in a housing. The display system may have a pixel array that produces light associated with images. The display system may also have a linear polarizer through which light from the pixel array passes and a quarter wave plate through which the light passes after passing through the quarter wave plate. The optical system may be a catadioptric optical system having one or more lens elements. The lens elements may include a plano-convex lens and a plano-concave lens. A partially reflective mirror may be formed on a convex surface of the plano-convex lens. A reflective polarizer may be formed on the planar surface of the plano-convex lens or the concave surface of the plano-concave lens. An additional quarter wave plate may be located between the reflective polarizer and the partially reflective mirror.

Abstract: A semiconductor structure comprises a first transistor and a second transistor. The first transistor comprises a first input source/drain region and a first output source/drain region, and the second transistor comprises a second input source/drain region and a second output source/drain region. The first input source/drain region and the second input source/drain region are connected to a first source/drain contact, and the first output source/drain region and the second output source/drain region are connected to a second source/drain contact. The first source/drain contact and the second source/drain contact on a same side of the semiconductor structure.

Abstract: A semiconductor structure including a gate contact above and in direct contact with a top surface of a gate. a backside wiring layer below a backside power delivery network. and a contact via extending between the gate contact and the backside wiring layer.

Abstract: A semiconductor device includes a dielectric isolation layer, a plurality of gates formed above the dielectric isolation layer, a plurality of source/drain regions above the dielectric isolation layer between the plurality of gates, and at least one contact placeholder for a backside contact. The at least one contact placeholder contacts a bottom surface of a first source/drain region of the plurality of source/drain regions. The semiconductor device further includes at least one backside contact contacting a bottom surface of a second source/drain region of the plurality of source/drain regions, and a buried power rail arranged beneath, and contacting the at least one backside contact.

Abstract: The present disclosure relates to an off-road vehicle having different features such as a frame having a frame structure, an engine assembly, an exhaust assembly, an engine mount assembly, a suspension assembly, a plurality of wheels, a hitch assembly, and other associated components. Embodiments of the present disclosure also describe a removable frame member facilitating the installation of the engine assembly from a seating area into a rearward portion of the vehicle. The off-road vehicle may further include an engine air intake assembly, an engine cooling assembly, a continuously variable transmission (CVT) cooling assembly, a vehicle cabin cooling assembly, a CVT housing assembly, a door assembly, a dashboard assembly, and other components.

Abstract: Embodiments of present invention provide an interconnect structure. The structure includes a metal line embedded in a dielectric layer; a first via intersecting with the metal line; and a second via intersecting with the metal line, the second via being horizontally separated from the first via by a length that is less than a blech length of the metal line, where the first and the second via extend vertically at least from a top surface of the metal line to a bottom surface of the metal line and have a width that is equal to or large than a width of the metal line. One or more method of forming the same are also provided.

Abstract: An ESD protection device is disclosed that uses a BSPDN to provide potential(s) to the ESD protection device. The utilization of the BSPDN reduces resistance drops induced during high current ESD events, which results in robust ESD protection. The utilization of the BSPDN also reduces the footprint area of the ESD protection circuit relative to known ESD protection devices that utilize respective frontside contacts to VDD, VSS, and I/O. Further, the disclosed ESD protection circuit may utilize the same or similar structures as that are used by microdevices (e.g., transistors, or the like) within the semiconductor IC device, which may decrease fabrication complexities thereof.

Abstract: An automated self-cleaning litter box (20) includes a guide arrangement (114) to allow for slidably mounting a disposable litter receptacle (40) The litter box can include a ramp (30) with a catch basin (142) and removable mat (146).

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a stack of transistors with a first transistor on top of a second transistor, where a gate of the first transistor has a first width; a gate of the second transistor has a second width; and the first width is narrower than the second width, and where the first and the second transistor respectively have a first gate extension at a first side of the stack and a second gate extension at a second side of the stack, the first gate extension at the first side of the stack being narrower than the second gate extension at the second side of the stack, with the first side being opposite the second side. A method of manufacturing the semiconductor structure is also provided.

Abstract: An air pocket is located between a top S/D region and a bottom S/D region of a stacked transistor. The air pocket reduces the parasitic capacitance between the top S/D region and the bottom S/D region, reduces the capacitance between the gate and the top S/D region, and/or reduces the capacitance between the gate and the bottom S/D region. Reduction of such capacitance(s) may improve performance of the semiconductor IC device and may allow for further semiconductor IC device scaling. A semiconductor IC device may include a bottom transistor and a top transistor. The top transistor may be vertically stacked, or aligned, with respect to the bottom transistor. The air pocket is located between, and may be vertically aligned with, the top S/D region and the bottom S/D region.

Abstract: A gate contact is formed within a gate cut region of a semiconductor structure to facilitate electrical routing. The gate contact includes a bottom portion extending within the gate cut region and adjoining a vertical end portion of a metal gate. A metal layer on the front side of the semiconductor structure includes signal tracks, one or more of which is vertically above the gate cut region. A signal track in the metal layer may be electrically connected to the gate contact. Selected source/drain regions within the semiconductor structure may be electrically connected to a back side power delivery network.

Abstract: A semiconductor structure is presented including a power rail having a non-rectangular shape and a middle-of-line (MOL) contact layer electrically connected to the power rail by a metal wiring layer. The non-rectangular shape of the power rail defines at least one notch. Alternatively, the non-rectangular shape of the power rail defines at least one extension. The power rail can be a via rail or a VARAIL.

Abstract: Semiconductor devices and methods of forming the same include a first layer including lower colinear vertical transfer field effect transistors (VTFETs). At least two of the colinear first VTFETs have a first shared bottom source/drain structure. A second layer is positioned over the first layer and includes upper colinear VTFETs. At least two of the upper colinear VTFETs have a second shared bottom source/drain structure.

Abstract: A microelectronic structure including a plurality of nanosheet transistors. Each of the plurality of nanosheet transistors includes an active gate located around a plurality of active channel layers and each of the plurality of nanosheet transistors includes a source/drain region have a first length. The first length is measured perpendicular to a gate direction of the plurality of nanosheet transistors. A power via located between a first dummy device and a second dummy device and the power via has second length. The second length is measured perpendicular to a gate direction of the plurality of nanosheet transistors. The second length is larger than the first length.

Abstract: A semiconductor device including a logic block, the logic block includes circuitry for one logic function of a semiconductor device, the logic block comprises a set of circuit rows, and a frontside to backside signal via vertically aligned and directly connecting a first backside metal signal to a first frontside metal signal, where the frontside to backside signal via is only in an edge cell of the logic block. A method including forming a logic block, the logic block includes circuitry for one logic function of a semiconductor device, the logic block comprises a set of circuit rows, and edge cells surrounding the logic block, forming a frontside to backside signal via vertically aligned and directly connecting a first backside metal signal to a first frontside metal signal, where the frontside to backside signal via is in an edge cell of the logic block.

Abstract: A semiconductor structure includes a first plurality of backside power rail interconnects located within a first cell height region of a substrate. A second plurality of backside power rail interconnects are located within a second cell height region of the substrate. A first isolation region is located between the first cell height region of the substrate and the second cell height region of the substrate. The first isolation region electrically separates the first cell height region and the second cell height region. A second isolation region is located between adjacent power rail interconnects of the first plurality of backside power rail interconnects and between adjacent power rail interconnects of the second plurality of backside power rail interconnects. The second isolation region electrically separates the adjacent power rail interconnects.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a metal level, the metal level includes a metal strip including a notch at a side of the metal strip or a pass-through inside the metal strip, wherein the notch or the pass-through is at least partially filled with a dielectric material. The metal level further includes a conductive wiring that vertically passes through the metal strip. The conductive wiring is at least partially inside the notch or inside the pass-through and is insulated from the metal strip by the dielectric material. Methods of manufacturing the semiconductor structure are also provided.

Abstract: A semiconductor structure includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, and wherein the isolation region extends through the top silicon layer to the BOX layer.