Patents by Inventor Brent Anderson

Brent Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10896972
    Abstract: Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having self-aligned contacts. In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source/drain region of a substrate. A conductive gate is formed over a channel region of the semiconductor fin. A top source/drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source/drain region. A dielectric cap is formed over the top metallization layer.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Steven Bentley, Su Chen Fan, Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie
  • Patent number: 10896857
    Abstract: Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Publication number: 20210005459
    Abstract: Methods for doping a semiconductor layer include forming a first mask on a first region of a semiconductor layer. A second region of the semiconductor layer, that is not covered by the first mask, is doped. A second mask is formed on the second region of the semiconductor layer. The first mask is etched away. The first region of the semiconductor layer is doped.
    Type: Application
    Filed: July 3, 2019
    Publication date: January 7, 2021
    Inventors: Junli Wang, Romain Lallement, Ardasheir Rahman, Liying Jiang, Brent A. Anderson
  • Publication number: 20200411682
    Abstract: Embodiments of the present invention are directed to a method for increasing the available width of a shallow trench isolation region. In a non-limiting embodiment of the invention, a semiconductor fin is formed over a substrate. A source or drain is formed on a surface of the substrate between the semiconductor fin and the substrate. A liner is formed over a surface of the semiconductor fin and a surface of the substrate is recessed to expose a sidewall of the source or drain. A mask is formed over the semiconductor fin and the liner. The mask is patterned to expose a top surface and a sidewall of the liner. A sidewall of the source or drain is recessed and a shallow trench isolation region is formed on the recessed top surface of the substrate. The shallow trench isolation region is adjacent to the recessed sidewall of the source or drain.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Ardasheir Rahman, Brent Anderson, JUNLI WANG, Stuart Sieg, Christopher J. Waskiewicz
  • Patent number: 10879112
    Abstract: A method of forming a via and a wiring structure formed are disclosed. The method may include forming a conductive line in a first dielectric layer; forming a hard mask adjacent to the conductive line after the conductive line forming; forming a second dielectric layer over the hard mask; and forming a via opening to the conductive line in the second dielectric layer. The via opening lands at least partially on the hard mask to self-align the via opening to the conductive line. A via may be formed by filling the via opening with a conductor.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: December 29, 2020
    Assignee: GlobalFoundries Inc.
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10876858
    Abstract: A device for use in a leak check test of an air data system includes a device body, an opening extending into the device body with the opening being configured to allow a probe to be at least partially inserted into the opening, and walls surrounding the opening with the walls being situated to seal a port in the probe such that air is prevented from flowing into or out of the port while the probe is inserted into the opening. A method of performing a leak check test includes covering the port with the device to seal the port, heating air within a gas path in the air data system, measuring the change in pressure of the air resulting from an increase in temperature of the air, and determining whether the air data system is sealed depending on the change in pressure of the air.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: December 29, 2020
    Assignee: Rosemount Aerospace Inc.
    Inventors: Brian Brent Naslund, Benjamin John Langemo, Matthew Paul Anderson, Andrew Sherman
  • Publication number: 20200397529
    Abstract: An immersive display for use in a robotic surgical system includes a support arm, a housing mounted to the support arm and configured to engage with a face of the user, at least two eyepiece assemblies disposed in the housing and configured to provide a three-dimensional display, and at least one sensor, wherein the sensor enables operation of the robotic surgical system, and wherein the support arm is actuatable to move the housing for ergonomic positioning.
    Type: Application
    Filed: September 1, 2020
    Publication date: December 24, 2020
    Inventors: Kent ANDERSON, Joan SAVALL, Brent NOBLES, Allegra SHUM, Pablo E. GARCIA KILROY, Karen Shakespear KOENIG
  • Patent number: 10840373
    Abstract: A semiconductor device includes a substrate having an input/output (IO) field-effect transistor (FET) device area, and an IO FET device formed in the IO FET device area. The IO FET device includes at least two fin structures separated by a distance associated with a length of a channel connecting the at least two fin structures. The length of the channel is determined based on at least one voltage for implementing the IO FET device.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xuefeng Liu, Junli Wang, Brent A. Anderson, Terence B. Hook, Gauri Karve
  • Patent number: 10832975
    Abstract: A method of reducing the distance between co-linear vertical fin field effect devices is provided. The method includes forming a first vertical fin on a substrate, forming a second vertical fin on the substrate, and depositing a masking block in the gap between the first vertical fin and second vertical fin. The method further includes depositing a spacer layer on the substrate, masking block, first vertical fin, and second vertical fin, depositing a protective liner on the spacer layer, and removing a portion of the protective liner from the spacer layer on the masking block and substrate adjacent to the first vertical fin. The method further includes removing a portion of the spacer layer from a portion the masking block and a portion of the substrate adjacent to the first vertical fin, and growing a first source/drain layer on an exposed portion of the substrate and first vertical fin.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Brent A. Anderson, Junli Wang, Kangguo Cheng, Choonghyun Lee, Hemanth Jagannathan
  • Patent number: 10823751
    Abstract: An aircraft probe includes a base, a strut that extends from the base, at least one port, and an electronics assembly insertable into the strut and removable from the strut. The electronics assembly includes at least one pressure sensor that is pneumatically connected to the at least one port to sense a first pressure when in the inserted position.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: November 3, 2020
    Assignee: Rosemount Aerospace Inc.
    Inventors: Brian Brent Naslund, Matthew Paul Anderson, Benjamin John Langemo, Andrew Sherman
  • Publication number: 20200335393
    Abstract: A method for fabricating a semiconductor device to account for misalignment includes forming a top via on a first conductive line formed on a substrate, forming liners each using a first dielectric material, including forming first and second liners to a first height along sidewalls of the top via, forming dielectric layers, including forming first and second dielectric layers on the first conductive line to the first height and adjacent to the first and second liners, respectively, recessing the top via to a second height, and forming an additional dielectric layer on the recessed top via to the first height using a second dielectric material. The first and second dielectric materials are selected to compensate for potential misalignment between the first conductive line and the top via.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 22, 2020
    Inventors: Chen Zhang, Lawrence A. Clevenger, Benjamin D. Briggs, Brent A. Anderson, Chih-Chao Yang
  • Patent number: 10811507
    Abstract: Embodiments of the invention are directed to configurations of semiconductor devices. A non-limiting example configuration includes a plurality of first transistors formed over a performance region of a major surface of a substrate. Each of the plurality of first transistors includes a first channel fin structure and a first gate structure along at least a portion of a sidewall surface of the first channel fin structure. The first gate structure includes a first gate thickness dimension. A plurality of second transistors is formed over a density region of the major surface of the substrate. Each of the plurality of second transistors includes a second channel fin structure and a second gate structure along at least a portion of a sidewall surface of the second channel fin structure, where the second gate structure includes a second gate thickness dimension that is less than the first gate thickness dimension.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: October 20, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Fee Li Lie, Stuart A. Sieg, Junli Wang
  • Patent number: 10809276
    Abstract: A system includes a probe, a transducer, and a sealing feature. The probe is detachable and includes a first gas path extending from a head to a mount. The transducer is configured to mate with the mount and includes a second gas path with an inlet configured to be in fluid communication with the outlet of the first gas path when the transducer is mated with the mount and at least one sensor disposed along the second gas path. The sealing feature includes a first membrane configured to allow pressure to be conveyed from the first gas path to the second gas path when the transducer is mated with the mount while preventing contaminants from entering the second gas path when the transducer is distant from the probe.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: October 20, 2020
    Assignee: Rosemount Aerospace Inc.
    Inventors: Brian Brent Naslund, Benjamin John Langemo, Matthew Paul Anderson, Andrew Sherman
  • Patent number: 10811508
    Abstract: Embodiments of the invention are directed to methods of forming a configuration of semiconductor devices. A non-limiting example method includes forming a first channel fin structure over a performance region of a major surface of a substrate. A first gate structure is formed along at least a portion of a sidewall surface of the first channel fin structure, where the first gate structure includes a first gate thickness dimension. A second channel fin structure is formed over a density region of the major surface of the substrate. A second gate structure is formed along at least a portion of a sidewall surface of the second channel fin structure, where the second gate structure includes a second gate thickness dimension that is less than the first gate thickness dimension.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: October 20, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Fee Li Lie, Stuart A. Sieg, Junli Wang
  • Patent number: 10811528
    Abstract: High breakdown voltage devices are provided. In one aspect, a method of forming a device having a VTFET and a LDVTFET includes: forming a LDD in an LDVTFET region; patterning fin(s) in a VTFET region to a depth D1; patterning fin(s) in the LDVTFET region, through the LDD, to a depth D2>D1; forming bottom source/drains at a base of the VTFET/LDVTFET fins; burying the VTFET/LDVTFET fins in a gap fill dielectric; recessing the gap fill dielectric to full expose the VTFET fin(s) and partially expose the LDVTFET fin(s); forming bottom spacers directly on the bottom source/drains in the VTFET region and directly on the gap fill dielectric in the LDVTFET region; forming gates alongside the VTFET/LDVTFET fins; forming top spacers above the gates; and forming top source/drains above the top spacers. A one-step fin etch and devices having VTFET and long channel VTFETs are also provided.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: October 20, 2020
    Assignee: International Business Machines Corporation
    Inventors: Mona Ebrish, Xuefeng Liu, Brent Anderson, Huiming Bu, Junli Wang
  • Patent number: 10786327
    Abstract: An immersive display for use in a robotic surgical system includes a support arm, a housing mounted to the support arm and configured to engage with a face of the user, at least two eyepiece assemblies disposed in the housing and configured to provide a three-dimensional display, and at least one sensor, wherein the sensor enables operation of the robotic surgical system, and wherein the support arm is actuatable to move the housing for ergonomic positioning.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: September 29, 2020
    Assignee: Verb Surgical Inc.
    Inventors: Kent Anderson, Joan Savall, Brent Nobles, Allegra Shum, Pablo E. Garcia Kilroy, Karen Shakespear Koenig
  • Patent number: 10777659
    Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes at least a n-type vertical FET and a p-type vertical FET. The n-type vertical FET includes at least a first bottom source/drain layer. The p-type vertical FET includes at least a second bottom source/drain layer. A silicon dioxide layer separates the first bottom source/drain layer and the second bottom source/drain layer. The method includes forming a first bottom source/drain layer in a p-type vertical FET device area. A germanium dioxide layer is formed in contact with the first semiconductor layer a second semiconductor fin formed within a n-type vertical FET device area. A silicon dioxide layer is formed in contact with the first bottom source/drain layer from the germanium dioxide layer. A second bottom source/drain layer is formed in contact with the second semiconductor fin and the silicon dioxide layer.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Ruqiang Bao, Shogo Mochizuki, Brent A. Anderson, Hemanth Jagannathan
  • Patent number: 10777469
    Abstract: Semiconductor devices and methods of forming the same include forming a doped dielectric layer on a semiconductor fin. The doped dielectric layer is annealed to drive dopants from the doped dielectric layer into the semiconductor fin. A gate stack is formed on the semiconductor fin.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: September 15, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Junli Wang, Brent A. Anderson, Xin Miao
  • Patent number: 10755017
    Abstract: A computer-implemented method of cell placement is provided. The method includes representing a non-rectangular cell to be placed into a cell row and searching the cell row to identify existing objects that are representative of cells in the cell row that are disposable to share space with the non-rectangular cell. The method further includes determining whether a representation of the non-rectangular cell is fittable into a modified mapping of the existing objects in the cell row and, in an event the representation is fittable into the modified mapping, overlapping the representation over one or more of the portions of the existing objects.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Laura R. Darden, Albert M. Chu, Alexander J. Suess
  • Patent number: 10742218
    Abstract: A semiconductor structure includes a vertical transport logic circuit cell. The vertical transport logic cell includes a first logic gate and at least a second logic gate. The first logic gate includes at least one input terminal and at least one output terminal. The second logic gate includes at least one input terminal and at least one output terminal. One of the input terminal and the output terminal of the first logic gate shares a pitch of the vertical transport logic circuit cell with one of the input terminal and the output terminal of the second logic gate. The first and second logic gates can include the same type or different types of logic functions.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corpoartion
    Inventors: Brent A. Anderson, Albert Chu